XILINX 2020.1自制IP导入vitis编译工程报错，修改makefile

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Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.1 (64-bit)

Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=…/…/…/lib
INCLUDEDIR=…/…/…/include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=$(wildcard *.h)
LIBSOURCES=$(wildcard *.c *.cpp)
OUTS = $(addsuffix .o, $(basename $(wildcard *.S))) 
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c *.cpp)))
ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))

libs:
echo “Compiling mnist_nn_predict”
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r $RELEASEDIR/${LIB} $(OUTS)
make clean

include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)

clean:
rm -rf ${OUTS}

代码块中内容为已修改代替内容
网上大部分是说需要改动四个地方，不知道为什么我这边改了四个。。。
分别是hw、psu_cortexa53_0、zynqmp_fsbl和zynqmp_pmufw