hdlbits_Fsm_serial

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
	parameter stop = 0,b0=1,b1=2,b2=3,b3=4,b4=5,b5=6,b6=7,b7=8,stop_ok=9,stop_notok=10,start = 11;
    //parameter idle = 0,start = 1,b0=2,b1=3,b2,=4,b3,b4,b5,b6,b7,stop;
    reg [4:0]state ,next;
    
    always @(*)
        begin
            case(state)
                stop:next = (~in)? start:stop;
                start: next = b0;
                b0: next =b1;
                b1: next = b2;
                b2: next = b3;
                b3: next = b4;
                b4: next = b5;
                b5: next = b6;
                b6: next = b7;
                b7: next = in?stop_ok:stop_notok;
                //stop: next = in?stop_ok: idle;
                stop_ok: next = (~in)?start:stop;
                stop_notok: next = in?stop:stop_notok;
            endcase
        end
    
    always @(posedge clk)
        begin
            if (reset)
                state <= stop;
            else
                state <= next;
        end
    
    assign done =(state ==stop_ok);
endmodule