[HDLBits] Exams/2013 q2bfsm

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    //a为初始态，00结尾、10结尾和1结尾分别出状态，以及y为0，01，1,00的状态
    parameter a=0,b=1,end_with_1=2,s10=3,s00=4,ydefault=5,y0=6,y1=7,y1_final=8,y0_final=9;
    wire [3:0] state,next;
    //reg flag;
    always@(*) begin
        case(state)
            a:next=resetn?b:a;
            b:next=s00;
            end_with_1:next=x?end_with_1:s10;
            s10:next=x?ydefault:s00;
            s00:next=x?end_with_1:s00;
            ydefault:next=y?y1:y0;
            y0:next=y?y1_final:y0_final;
            y1:next=y1_final;
            y1_final:next=y1_final;
            y0_final:next=y0_final;
        endcase
    end
    always@(posedge clk) begin
        if(!resetn) 
            state<=a;
        else
            state<=next;
    end
    assign f=state==b;
    assign g=(state==ydefault)||(state==y0)||(state==y1)||(state==y1_final);
endmodule
//这题倒是不难，但是他说的什么下个clk置为1这种描述不太清晰，不好理解