【关于FPGA内部die到pin的延时数据，即pin delay获取方法】
首先，本文只介绍Xilinx的，Alteral的以后。。
第一，生成平台
Xilinx目前在用的是ISE,和Vivado；二者之间并不是可以互相替代的，或者说这两者不完全是迭代的关系。
第二，先介绍常用的–VIVADO
这里又有几种方法
①不管是windows平台还是linux平台，首先可以使用非工程模式，即TCL模式；
****** Vivado v2050.1 (256-bit)
**** SW Build 2908876 on Wed Nov 6 21:40:23 MST 2050
**** IP Build 2900528 on Thu Nov 7 00:09:20 MST 2050
** Copyright 1986-2050 Xilinx, Inc. All Rights Reserved.
Vivado%
输入
link_design -part xcku15p-ffve1517-2-i
later
Command: link_design -part xcku15p-ffve1517-2-i
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xcku15p-ffve1517-2-i
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1603.305 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1605.258 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1605.258 ; gain = 1312.551
design_1
Vivado%
最后一步
Vivado%write_csv xcku15p-ffve1517.csv
最后就可以去找文件
xcku15p-ffve1517.csv
pin delay 也即是Trace Delay
数据有下图
②打开vivado ,使用工程模式，或者说窗口下，依然是TCL命令；
输入的命令同①，不在介绍。
第三，先介绍不常用的–ISE
ISE14.7的窗口画面并不集成tcl脚本；
所以，windows去程序列表搜索【ISE Design Suite 64 Bit Command Prompt】;Linux 配置环境变量，去到/opt/… 14.7/ISE_DS路径下：
键入命令：
PARTGen -v xc6vcx130tff784
输出结果：
C:\Xilinx\14.7\ISE_DS>PARTGen -v xc6vcx130tff784
Release 14.7 - PartGen P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6vcx130t.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
这时候；就完成了，打开当前路径的xc6vcx130tff784.pkg
pin delay 也即是Trace Delay
以上参考：
① UG628 (v14.7) October 2, 2013 Page33;
② https://support.xilinx.com/s/article/55697?language=en_US
We do not give trace length data, but rather give the delay in time, as it is the most accurate way to estimate true package delay.
1) Open any design in Vivado, either RTL, Netlist or Implemented. Then select Export > I/O Ports > CSV.
You will see all of the min and max package delays for each pin.
The min/max trace delays are also displayed in the Package Pins window for every package pin within two separate columns.
Similarly you can select File->Export I/O ports to get a CSV type spreadsheet with the delays included.
2) If there is no project you can use the following Tcl commands:
link_design -part <part_number>
write_csv <file_name>
For Example:
link_design -part xc7k410tffg900-2
write_csv flight_time
③ 22814 - 14.x Timing Analysis - How do I calculate the flight time for my device?
····https://support.xilinx.com/s/article/22814?language=en_US
For 7 series and newer, partgen gives flight time numbers not delay values.
For pre 7 series devices, you can calculate the trace lengths by running the partgen command. To run the partgen command:
1. Open a DOS command or shell prompt. (note that in 12.x and beyond there is a Xilinx specific command prompt short cut in the accessories folder)
2. Type : partgen -v {part that you need to use} 4vlx25ff668.
3. This creates a dot pkg file with the trace length in microns for each pin in it.
To convert the trace length from microns to flight time:
1. Open the dot pkg file in a text editor. The column on the far right is the trace length in microns.
2. Convert the micron to a millimeter (trace length / 1000).
3. The delay through this is 6.0 - 7.1 ps/mm.
For example:
5610 microns = 5.61 millimeters
5.61 millimeters = 33.66 - 39.83 ps
This is provided only for the Flip-Chip packages. For more information on other parts, see (Xilinx Answer 18078).
Improved precision in flight time through package calculation can be found at (Xilinx Answer 34174).
④ https://support.xilinx.com/s/article/21632?language=en_US
When using the custom IBIS file (IBISWriter utility):
a) A design specific custom IBIS file is generated from IBISWriter (available as part of the ISE design environment), IBISWriter takes in a design implementation (.ncd) file, and IBISWriter outputs a custom/design specific IBIS file ready for simulation.
b) Per pin package parasitic data (if available) can be included in the custom IBIS file.
i) From the Command line: use the -pin option or manually insert into the custom IBIS file as described in paragraph 1.b.ii above.
ii) Within the ISE GUI:
In the Processes window:
Expand the Implement design tree.
Expand the Place and Route tree.
Right-click Generate IBIS Model and select Properties.
Enable checkbox Generate Detailed Package Parasitics.
Double-click Generate IBIS Model to create to output file.
c) To ensure the custom/design specific IBIS file contains the latest I/O model and package parasitic data:
i) For Virtex 4 and Virtex 5, run XilinxUpdate prior to the launch of IBISWriter. XilinxUpdate can synchronize the data file under the ISE database with the latest IBIS data available in the Xilinx download center.
ii) For other devices, if the IBIS data in the Xilinx download center is updated after an ISE release, then the IBISWriter utility cannot be used and you must configure the I/O model and package model manually with the steps below:
Download the latest available IBIS model from the download center.
Manual update of the I/O model:
-- For all models used in your design, look for the [Model] keyword, and copy everything until the next [Model] keyword.
-- Annotate the pin list to link each I/O pin using the new I/O model: Look for the [Pin] keyword. For all I/Os in your design if it is not already listed, then add a reference to it here; if it is already listed, verify that it references the appropriate model.
In this section, there should be one line per package pin. Syntax is: < pin number > < user-supplied pin name > < model name as defined by the [Model] keyword >.
Manual updates of the package model:
-- Process is described in paragraph 1.b above.