USB 2.0 Host0 控制器 (EHCI & OHCI) 的DTS为例:
其中,EHCI 控制器的 compatible 固定为 “generic-ehci”,OHCI 控制器的 compatible 固定为 “genericohci”。并且,EHCI 和 OHCI 复用同样的 clocks 和 phys。属性 “power-domains” 并不是每种芯片都需要配 置,只有当芯片的 USB 2.0 Host 控制器支持 power-domains 功能时,才需要配置该属性。
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = ;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&cru SCLK_USBPHY0_480M_SRC>;
clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
phys = <&u2phy0_host>;
phy-names = "usb";
power-domains = <&power RK356x_PD_PERIHP>;
status = "disabled";
};
usb_host0_ohci: usb@fe3a0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = ;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&cru SCLK_USBPHY0_480M_SRC>;
clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
phys = <&u2phy0_host>;
phy-names = "usb";
power-domains = <&power RK356x、_PD_PERIHP>;
status = "disabled";
};
RK356x HOST2 第DTS节点名称定义如下:
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
usb20_otg: usb@ff580000 {
compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = ;
clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
clock-names = "otg", "otg_pmu";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
dr_mode:必须配置为 "host", "peripheral" 或者 "otg";
g-rx-fifo-size:配置 Gadget mode 的 rx fifo 大小;
g-np-tx-fifo-size:配置 Gadget mode 的 non-periodic tx fifo 大小;
g-tx-fifo-size:配置 Gadget mode 的每个 IN 端点的 tx fifo 大小(端点 0 除外);
g-use-dma:使能 Gadget 驱动使用 DMA 传输;
phys:配置 PHY 节点;
phy-names: 必须配置为 "usb2-phy".
USB 3.0 Host 控制器为 xHCI,集成于 DWC3 OTG IP 中,所以不用单独配置 dts,只需要配置 DWC3 节 点,并且设置 DWC3 的 dr_mode 属性为 dr_mode = "otg"或者 dr_mode = "host",就可以使能 xHCI 控制 器。
usbdrd3_0: usb0 {
compatible = "rockchip,rk3399-dwc3";
clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "grf_clk";
power-domains = <&power RK3399_PD_USB3>;
resets = <&cru SRST_A_USB3_OTG0>;
reset-names = "usb3-otg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbdrd_dwc3_0: dwc3@fe800000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = ;
dr_mode = "otg";
phys = <&u2phy0_otg>, <&tcphy0_usb3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,tx-ipgap-linecheck-dis-quirk;
snps,xhci-slow-suspend-quirk;
snps,xhci-trb-ent-quirk;
snps,usb3-warm-reset-on-resume-quirk;
status = "disabled"; };
};
USB 3.0 OTG DTS 包含了父节点 “usbdrd3_0” 和子节点 “usbdrd_dwc3_0”。其中,除了 RK3328/RK3228H外,所有支持 DWC3 控制器的芯片,父节点的 compatible 都要加上 “rockchip,rk3399-dwc3”。所有芯片的 子节点 compatible 都配置为 “snps,dwc3”。父节点的作用是,配置芯片级相关的属性,如:clocks,power-domains,reset。子节点的作用是,配置控制器相关的属性,其中的 quirk 属性,适用于所有芯片 的 DWC3 控制器。