讲解：CSCI 2121、Assembly Language、Python，c/c++、Java，PythonSQ

CSCI 2121: Computer Organization andAssembly LanguageLab 4Design Sequential Circuits in Verilog IIThursday 14th February, 20191 Learning Objectives In this lab, you will learn to interpret Verilog for testbenches. You will learn case statements, serial and parallel data transfer. You will implement a vending machine.2 Submission Instruction Save code for each task as .sv file, with the name specified at the end of each lab task. Put all lab files into one folder, and compress the folder to a .zip file. Submit it on Brightspace. Deadline for submission: Sunday 17th February, 2019, 11:55 pm. As the marking will be done automatically by a script, it is important that you followthese instructions and save your files with correct names and .sv extension.13 Lab Assignment3.1 Lab Task 1: Frequency DividerA frequency divider takes only a clock as input, which constantly alternates producing 1and 0, and produces a lower frequency alternating signal. We will make a circuit to quarter theinput rate. Every time the clock pulses four times, we would like to set our output to be theopposite of the current output. To do this, we will negate our output when the clock’s stateis 0. In order to keep track of four clock pulses, we need two state bits. The skeleton code isavailable at https://www.eda代写CSCI 2121作业、代做Assembly Language作业、Python，c/c++程序作业代写、代做Javplayground.com/x/5hDr. Name your file as task1.svHint: you can use either if. . . else, or case, or (ternary operator) to complete the alwaysblock.3.2 Lab Task 2: Vending MachineUsing previous knowledge of sequential circuits, you will now construct a vending machinecontroller according to the following specifications. The circuit has four inputs: clk, quarter,loonie, and toonie. The controller also has two outputs: change and dispense. Changeis a 3-bit bus which outputs a binary number indicating the number of quarters to dispense.Dispense is a single on/off wire. You must implement the controller based on the followingproperties. The skeleton code is available at https://www.edaplayground.com/x/2at. Nameyour file as task2.sv1. The item (and change, if any) is dispensed when $1 is inserted into the machine.2. Change outputs a binary number indicating the number of quarters to dispense.3. The dispense and change signals are set to 1 on the same clock tick that the amount ismet.Note: In the lecture, you designed sequential circuits using 6 steps from specification tominimizing the circuit. In Verilog, however, you need to mainly focus on the specification andthe state transition diagram. The rest of the circuit design is done with high-level Verilogstatements.Figure 1: Vending Machine转自：http://ass.3daixie.com/2019021676271540.html