设计数据(LEF/DEF/netlist)、cpf文件、SPEF文件
方法一:读入.dat数据
read_design -physical_data postroute.enc.dat design_name
方法二:读入def文件
set lefs [list]
lappend lefs a.lef
lappend lefs b.lef
read_lib -lef $lefs
read_view_definition viewDefinition.tcl
read_verilog design.v.gz
set_top_module design_name -ignore_undefined_cell
read_def design_name.def.gz
方法一:读入CPF文件
read_power_domain -cpf design_name.cpf
方法二:定义每个 power/ground net's 电压
set_dc_sources VDD_A0 -power -voltage 0.9 -force
set_dc_sources VDD_external -power -voltage 0.9 -force
set_dc_sources VSS -ground
方法三:不存在cpf时定义power nets 并设置属性
set_pg_nets -net VSS -voltage 0.0 -threshold 0.05
set_pg_nets -net VDD -voltage 1.5 -threshold 1.425
set_rail_analysis_domain -name PD1 -pwrnets VDD -gndnets VSS
read_spef -rc_corner corner_name -decoupled coener_name.spef.gz
4.设计数据检查(design sanity check)
1)check design
检查的内容:物理库、时序库、网表、I/Os、tie-high&tie-low pins、电源/地pins
check_design -out_file checkDesign -type {power_intent timing hierarchical pin_assign budget assign_statements place opt cts route signoff all}
2) check timing library
check_library -outfile design.tallib -checkpower -reportMissingPowerOnly
3)verify connectivity
检查内容:
verify_connectivity -type special -error 1000 -warning 50 -report dma_mac.conn.rpt
4)verify power via
检查内容:
verify_power_via -report power_via.report
5)verify power and ground shorts
检查内容:
verify_PG_short -net {VDD VSS}