野火开发板【紫光FPGA】

时钟引脚:		
FPGA_CLK_50M	B5	
		
按键引脚:		
RESET	E8	
KEY1	K18	
KEY2	N17	
KEY3	N18	
KEY4	H17	

LED灯引脚:		
LED1	D15	
LED2	C15	
LED3	A12	
LED4	B12	

无源蜂鸣器引脚:
BEEP	H13	

USB转串口引脚:		
UART1_RX	A15	
UART1_TX	B15	

以太网引脚:		
ETH_RXD0	A17
ETH_RXD1	B17
ETH_RXD2	G17
ETH_RXD3	G18
ETH_RX_CLK	E17
ETH_RX_CTL	E18
ETH_TXD0	G11
ETH_TXD1	F11
ETH_TXD2	E16
ETH_TXD3	E15
ETH_TX_CTL	C10
ETH_TX_CLK	D10
ETH_MDC	    E16
ETH_MDIO	E15
ETH_INIB	A1
ETH_NRST	B1

EEPROM各引脚:		
I2C_SCL	D13	
I2C_SDA	C13	
		
FLASH各引脚分配如下表所示:		
引脚名	FPGA绑定引脚	
QSPI_CS	B8	
QSPI_CLK	C9	
QSPI_IO0	B4	
QSPI_IO1	A4	
QSPI_IO2	B3	
QSPI_IO3	A3	
		
		
		
DDR3 SDRAM各引脚分配如下表所示:		
引脚名	FPGA绑定引脚	
DDR3_A0	M4	
DDR3_A1	M3	
DDR3_A2	P2	
DDR3_A3	P1	
DDR3_A4	L5	
DDR3_A5	M5	
DDR3_A6	N2	
DDR3_A7	N1	
DDR3_A8	K4	
DDR3_A9	M1	
DDR3_A10	M6	
DDR3_A11	L1	
DDR3_A12	K2	
DDR3_A13	K1	
DDR3_A14	J2	
DDR3_BA0	U2	
DDR3_BA1	U1	
DDR3_BA2	T2	
DDR3_CSN	R1	
DDR3_RASN	R2	
DDR3_CASN	T1	
DDR3_WEN	V1	
DDR3_ODT	V2	
DDR3_CLK0_P	U3	
DDR3_CLK0_N	V3	
DDR3_CKE	L4	
DDR3_RESET	M2	
DDR3_D0	T8	
DDR3_D1	T6	
DDR3_D2	R6	
DDR3_D3	R9	
DDR3_D4	T9	
DDR3_D5	N4	
DDR3_D6	N5	
DDR3_D7	P6	
DDR3_D8	U7	
DDR3_D9	V6	
DDR3_D10	V7	
DDR3_D11	U6	
DDR3_D12	U9	
DDR3_D13	T4	
DDR3_D14	V9	
DDR3_D15	V5	
DDR3_DQS0_P	N6	
DDR3_DQS0_N	N7	
DDR3_DQS1_P	U8	
DDR3_DQS1_N	V8	
DDR3_DM0	R8	
DDR3_DM1	U5	
		

		

		
		

	HDMI引脚分配如下表所示:		
	引脚名	FPGA绑定引脚	
	HDMI_TX0_P	E1	
	HDMI_TX0_N	E2	
	HDMI_TX1_P	D1	
	HDMI_TX1_N	D2	
	HDMI_TX2_P	C1	
	HDMI_TX2_N	C2	
	HDMI_TXC_P	E5	
	HDMI_TXC_N	E6	
	HDMI_CEC	A11	
	HDMI_EN	B10	
	HDMI_HPD	F13	
	HDMI_SCL	B11	
	HDMI_SDA	A10	
			

	     LCD引脚分配如下表所示:		
	引脚名	FPGA绑定引脚	
	LCD_BL	L12	
	CTP_RST	L13	
	CTP_INT	F18	
	LCD_SDA	F17	
	LCD_SCL	H18	
	LCD_VS	J14	
	LCD_HS	K14	
	LCD_DE	J15	
	LCD_CLK	K15	
	LCD_R0	U14	
	LCD_R1	V14	
	LCD_R2	U15	
	LCD_R3	V15	
	LCD_R4	V16	
	LCD_R5	U16	
	LCD_R6	L15	
	LCD_R7	L14	
	LCD_G0	N16	
	LCD_G1	T16	
	LCD_G2	N15	
	LCD_G3	R16	
	LCD_G4	L16	
	LCD_G5	M16	
	LCD_G6	V18	
	LCD_G7	V17	
	LCD_B0	U18	
	LCD_B1	U17	
	LCD_B2	T18	
	LCD_B3	T17	
	LCD_B4	R17	
	LCD_B5	R18	
	LCD_B6	P17	
	LCD_B7	P18	
			
			
	     SD卡引脚分配如下表所示:		
	引脚名	FPGA绑定引脚	
	SD_CLK	M18	
	SD_CMD	M17	
	SD_CD	K17	
	SD_DATA0	J17	
	SD_DATA1	J18	
	SD_DATA2	L17	
	SD_DATA3	L18	
			
			
	        摄像头接口引脚分配如下表所示:		
	引脚名	FPGA绑定引脚	
	CAM_PDN	A14	
	CAM_RST	B14	
	CAM_CLKIN	A18	
	CAM_PCLK	B18	
	CAM_VS	C17	
	CAM_HS	C18	
	CAM_D0	A13	
	CAM_D1	B13	
	CAM_D2	J16	
	CAM_D3	H16	
	CAM_D4	G16	
	CAM_D5	F16	
	CAM_D6	G13	
	CAM_D7	G14	
	CAM_SCL	D17	
	CAM_SDA	D18	
			
			
			



你可能感兴趣的:(FPGA,fpga开发)