Verilog刷题HDLBits——Exams/m2014 q4k

题目描述

Implement the following circuit:

代码

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    reg[3:0] q;
    always@(posedge clk)
        begin
            if(~resetn)
                q<=0;
            else
                q<={q[2:0],in};
        end
    assign out = q[3];

endmodule

结果