Sequential Logic
Latches and Flip-Flops
module top_module (
input clk,
input d,
output reg q );
always @ (posedge clk) begin
q <= d;
end
endmodule
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @ (posedge clk) begin
q <= d;
end
endmodule
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @ (posedge clk) begin
if (reset)
q <= 0;
else
q <= d;
end
endmodule
-
DFF with reset value
题目链接
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @ (negedge clk) begin
if (reset)
q <= 8'h34;
else
q <= d;
end
endmodule
-
DFF with asynchronous reset
题目链接
module top_module (
input clk,
input areset,
input [7:0] d,
output [7:0] q
);
always @ (posedge clk or posedge areset) begin
if (areset)
q <= 0;
else
q <= d;
end
endmodule
-
DFF with byte enable
题目链接
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @ (posedge clk) begin
if (~resetn) begin
q <= 16'b0;
end
else begin
q <= {(({8{byteena[1]}} & d[15:8]) | ({8{~byteena[1]}} & q[15:8])), (({8{byteena[0]}} & d[7:0]) | ({8{~byteena[0]}} & q[7:0]))};
end
end
endmodule
module top_module (
input d,
input ena,
output q);
reg q_reg;
assign q = q_reg;
always @ (*) begin
if (ena)
q_reg <= d;
end
endmodule
module top_module (
input clk,
input d,
input ar,
output q);
always @ (posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
module top_module (
input clk,
input d,
input r,
output q);
always @ (posedge clk) begin
if (r) begin
q <= 0;
end
else begin
q <= d;
end
end
endmodule
module top_module (
input clk,
input in,
output out);
always @ (posedge clk) begin
out <= (in ^ out);
end
endmodule
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
wire ff_in = L ? r_in : q_in;
always @ (posedge clk) begin
Q <= ff_in;
end
endmodule
module top_module (
input clk,
input w, R, E, L,
output Q
);
wire ff_in_1 = E ? w : Q;
wire ff_in = L ? R : ff_in_1;
always @ (posedge clk) begin
Q <= ff_in;
end
endmodule
module top_module (
input clk,
input x,
output z
);
reg Q_ff1 = 0, Q_ff2 = 0, Q_ff3 = 0;
wire D_ff1, D_ff2, D_ff3;
assign D_ff1 = x ^ Q_ff1;
assign D_ff2 = ~Q_ff2 & x;
assign D_ff3 = ~Q_ff3 | x;
assign z = ~(Q_ff1 | Q_ff2 | Q_ff3);
always @ (posedge clk) begin
Q_ff1 <= D_ff1;
Q_ff2 <= D_ff2;
Q_ff3 <= D_ff3;
end
endmodule
-
Create circuit from truth table
题目链接
module top_module (
input clk,
input j,
input k,
output Q);
reg Q_old;
always @ (posedge clk) begin
case({j,k})
2'b00: Q <= Q_old;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q_old;
endcase
end
always @ (*) begin
Q_old <= Q;
end
endmodule
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] in_old = 8'b0;
always @ (posedge clk) begin
pedge <= (in & ~in_old);
in_old <= in;
end
endmodule
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] in_old;
always @ (posedge clk) begin
anyedge <= in_old ^ in;
in_old <= in;
end
endmodule
-
Edge capture register
题目链接
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out = 32'b0
);
reg [31:0] in_old = 32'b0;
reg [31:0] out_last = 32'b0;
always @ (posedge clk) begin
if (reset) begin
out <= 'b0;
end
else begin
out <= (in_old & ~in) | out_last;
end
in_old <= in;
end
always @ (*) begin
out_last <= out;
end
endmodule
-
Edge capture register
题目链接
module top_module (
input clk,
input d,
output q
);
reg q_1, q_2;
assign q = clk ? q_1 : q_2;
always @ (posedge clk) begin
q_1 <= d;
end
always @ (negedge clk) begin
q_2 <= d;
end
endmodule
Counters
-
Four-bit binary counter
题目链接
module top_module (
input clk,
input reset,
output [3:0] q);
always @ (posedge clk) begin
q = ({q + 1} % 16) & {4{~reset}};
end
endmodule
module top_module (
input clk,
input reset,
output [3:0] q);
always @ (posedge clk) begin
q <= ({q + 1} % 10) & {4{~reset}};
end
endmodule
-
Decade counter again
题目链接
module top_module (
input clk,
input reset,
output [3:0] q);
always @ (posedge clk) begin
q <= ((q % 10 + 1) & {4{~reset}}) | ((4'b1) & {4{reset}});
end
endmodule
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
reg [3:0] q_last;
always @ (posedge clk) begin
case({reset, slowena})
2'b00: q <= q_last;
2'b01: q <= {q_last + 1} % 10;
2'b10: q <= 0;
2'b11: q <= 0;
endcase
end
always @ (*) begin
q_last <= q;
end
endmodule
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
);
assign c_enable = enable;
assign c_load = (reset | (enable & Q==12)) ? 1 : 0;
assign c_d = 4'b1;
count4 the_counter (clk, c_enable, c_load, c_d, Q );
endmodule
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
);
reg [3:0] Q[2:0];
reg [3:0] Q_last[2:0];
assign c_enable[0] = 1;
assign c_enable[1] = (Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
assign c_enable[2] = (Q[1] == 4'b1001 && Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
assign OneHertz = (Q[2] == 4'b1001 && Q[1] == 4'b1001 && Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
bcdcount counter0 (clk, reset, c_enable[0], Q[0]);
bcdcount counter1 (clk, reset, c_enable[1], Q[1]);
bcdcount counter2 (clk, reset, c_enable[2], Q[2]);
always @ (posedge clk) begin
Q_last[2:0] <= Q[2:0];
end
endmodule
-
4-digit decimal clock
题目链接
module top_module (
input clk,
input reset,
output [3:1] ena,
output [15:0] q);
assign ena[1] = (q[3:0]==4'd9);
assign ena[2] = (ena[1] & q[7:4]==4'd9);
assign ena[3] = (ena[2] & q[11:8]==4'd9);
always @ (posedge clk) begin
if(reset) begin
q <= 'b0;
end
else begin
case ({ena[1], ena[2], ena[3]})
3'b100: begin q[3:0] <= 0; q[7:4] <= q[7:4] + 1; end
3'b110: begin q[3:0] <= 0; q[7:4] <= 0; q[11:8] <= q[11:8] + 1; end
3'b111: begin q[3:0] <= 0; q[7:4] <= 0; q[11:8] <= 0; q[15:12] <= {q[15:12] + 1} % 10; end
default: begin q[3:0] <= q[3:0] + 1; end
endcase
end
end
endmodule
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
wire ss_3_0_inc = (ss[3:0] == 4'd9) ? 1 : 0;
wire ss_7_4_inc = (ss[7:4] == 4'd5 & ss_3_0_inc) ? 1 : 0;
wire mm_3_0_inc = (mm[3:0] == 4'd9 & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
wire mm_7_4_inc = (mm[7:4] == 4'd5 & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
wire hh_3_0_inc = (hh[3:0] == 4'd9 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
wire hh_7_4_inc = (hh[7:4] == 4'd1 & hh[3:0] == 4'd2 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
wire pm_rev = (hh[7:4] == 4'd1 & hh[3:0] == 4'd1 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
always @ (posedge clk) begin
if (reset) begin
hh[7:4] <= 'd1;
hh[3:0] <= 'd2;
mm[7:4] <= 'd0;
mm[3:0] <= 'd0;
ss[7:4] <= 'd0;
ss[3:0] <= 'd0;
pm <= 0;
end
else begin
if (pm_rev)
pm <= ~pm;
if (ena) begin
case ({hh_7_4_inc,hh_3_0_inc,mm_7_4_inc,mm_3_0_inc,ss_7_4_inc,ss_3_0_inc})
'b000001: begin
ss[3:0] <= 0; ss[7:4] <= ss[7:4] + 1;
end
'b000011: begin
ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= mm[3:0] + 1;
end
'b000111: begin
ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= mm[7:4] + 1;
end
'b001111: begin
ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= hh[3:0] + 1;
end
'b011111: begin
ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= 0; hh[7:4] <= hh[7:4] + 1;
end
'b101111: begin
ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= 1; hh[7:4] <= 0;
end
default: begin
ss[3:0] <= ss[3:0] + 1;
end
endcase
end
end
end
endmodule
Shift Registers
-
4-bit shift register
题目链接
module top_module(
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always @ (posedge clk, posedge areset) begin
if (areset) begin
q <= 'b0;
end
else begin
if (load) begin
q <= data;
end
else if (ena) begin
q <= {1'b0,q[3:1]};
end
end
end
endmodule
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always @ (posedge clk) begin
if (load)
q <= data;
else
case (ena)
2'b01: q <= {q[0], q[99:1]};
2'b10: q <= {q[98:0], q[99]};
default: ;
endcase
end
endmodule
-
Left/right arithmetic shift by 1 or 8
题目链接
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @ (posedge clk) begin
if (load)
q <= data;
else
if(ena)
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <= {{8{q[63]}}, q[63:8]};
endcase
end
endmodule
module top_module(
input clk,
input reset,
output [4:0] q
);
always @ (posedge clk) begin
if (reset) begin
q <= 5'h1;
end
else begin
q[4] <= q[0] ^ 1'b0;
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
module top_module (
input [2:0] SW,
input [1:0] KEY,
output [2:0] LEDR);
always @ (posedge KEY[0]) begin
case (KEY[1])
0: begin
LEDR[0] <= LEDR[2];
LEDR[1] <= LEDR[0];
LEDR[2] <= LEDR[1] ^ LEDR[2];
end
1: begin
LEDR[0] <= SW[0];
LEDR[1] <= SW[1];
LEDR[2] <= SW[2];
end
endcase
end
endmodule
module top_module(
input clk,
input reset,
output [31:0] q
);
always @ (posedge clk) begin
if (reset)
q <= 32'h1;
else begin
q <= {1'b0 ^ q[0], q[31:23], q[22] ^ q[0], q[21:3], q[2] ^ q[0], q[1] ^ q[0]};
end
end
endmodule
module top_module (
input clk,
input resetn,
input in,
output out);
reg [3:0] shiftreg;
assign out = shiftreg[3];
always @ (posedge clk) begin
if (~resetn) begin
shiftreg <= 4'b0;
end
else begin
shiftreg <= {shiftreg[2:0], in};
end
end
endmodule
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
);
MUXDFF MUXDFF_3(KEY[0], KEY[3], SW[3], KEY[1], KEY[2], LEDR[3]);
MUXDFF MUXDFF_2(KEY[0], LEDR[3], SW[2], KEY[1], KEY[2], LEDR[2]);
MUXDFF MUXDFF_1(KEY[0], LEDR[2], SW[1], KEY[1], KEY[2], LEDR[1]);
MUXDFF MUXDFF_0(KEY[0], LEDR[1], SW[0], KEY[1], KEY[2], LEDR[0]);
endmodule
module MUXDFF (
input clk,
input w, R, E, L,
output Q
);
wire ff_in_1 = E ? w : Q;
wire ff_in = L ? R : ff_in_1;
always @ (posedge clk) begin
Q <= ff_in;
end
endmodule
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] Q;
assign Z = Q[{A, B, C}];
always @ (posedge clk) begin
if (enable) begin
Q <= {Q[6:0],S};
end
end
endmodule
More Circuits
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always @ (posedge clk) begin
if (load) begin
q <= data;
end
else begin
q <= {q[510:0], 1'b0} ^ {1'b0, q[511:1]};
end
end
endmodule
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @ (posedge clk) begin
if (load)
q <= data;
else
q <= (~q & {q[510:0],1'b0}) | (~{1'b0,q[511:1]} & {q[510:0],1'b0}) | (q & ~{q[510:0],1'b0});
end
endmodule
* ### Conway's Game of Life 16x16 [题目链接]() ## Finite State Machines
