Verilog刷题笔记4

题目：

Given an 8-bit input vector [7:0], reverse its bit ordering. See also:
Reversing a longer vector.

我的解法：

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out[7]=in[0];
    assign out[6]=in[1];
    assign out[5]=in[2];
    assign out[4]=in[3];
    assign out[3]=in[4];
    assign out[2]=in[5];
    assign out[1]=in[6];
    assign out[0]=in[7];
endmodule

结果正确：

学习解法：

module top_module(
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]} ;
endmodule

integer i;
always @ (*) begin
    for(i = 0; i < 8; i = i + 1)
        out[i] = in[7-i];
end

generate
    genvar i;
    for(i = 0; i < 8; i = i + 1) begin: my_block_name
        assign out[i] = in[7-i];
    end        
endgenerate