【xilinx primitives 】02 OBUFDS and OBUFTDS

参考源:

< UG471 7 Series FPGAs SelectIO Resources User Guide >

OBUFDS【xilinx primitives 】02 OBUFDS and OBUFTDS_第1张图片

该设计元件是单输出缓冲器,支持低电压、差分信号。
OBUFDS隔离内部电路,并为离开芯片的信号提供驱动电流。
它的输出表示为两个不同的端口(O 和 OB),
一个认为是“主端口”,另一个是“从端口”。
主端口和从端口是同一逻辑信号(例如,MYNET 和 MYNETB)的相反相位。

真值表

【xilinx primitives 】02 OBUFDS and OBUFTDS_第2张图片

例化

VHDL

Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFDS: Differential Output Buffer
--         7 Series
-- Xilinx HDL Language Template, version 2022.2
OBUFDS_inst : OBUFDS
generic map (
   IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
   SLEW => "SLOW")          -- Specify the output slew rate
port map (
   O => O,     -- Diff_p output (connect directly to top-level port)
   OB => OB,   -- Diff_n output (connect directly to top-level port)
   I => I      -- Buffer input
);
-- End of OBUFDS_inst instantiation

Verilog

// OBUFDS: Differential Output Buffer
//         7 Series
// Xilinx HDL Language Template, version 2022.2
OBUFDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I)      // Buffer input
);
// End of OBUFDS_inst instantiation

OBUFTDS【xilinx primitives 】02 OBUFDS and OBUFTDS_第3张图片

增加了3态门控制;

真值表

【xilinx primitives 】02 OBUFDS and OBUFTDS_第4张图片

例化

VHDL

Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFTDS: Differential 3-state Output Buffer
--          7 Series
-- Xilinx HDL Language Template, version 2022.2
OBUFTDS_inst : OBUFTDS
generic map (
   IOSTANDARD => "DEFAULT")
port map (
   O => O,     -- Diff_p output (connect directly to top-level port)
   OB => OB,   -- Diff_n output (connect directly to top-level port)
   I => I,     -- Buffer input
   T => T      -- 3-state enable input
);
-- End of OBUFTDS_inst instantiation

Verilog

// OBUFTDS: Differential 3-state Output Buffer
//          7 Series
// Xilinx HDL Language Template, version 2022.2
OBUFTDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFTDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input
);
// End of OBUFTDS_inst instantiation

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