累加器代码

module counter (co, reset, data, ci, clk);
parameter N=4;
output co;
input reset, ci, clk;
input[N-1:0]data;
reg [N-1:0] q ;
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always @(posedge clk)
begin
if (reset) q<=0;//
else
if(ci) q<=q + 1;

end
assign co=(q==data-1) && ci; //
endmodule