AD9361纯逻辑控制从0到1连载3-初始化模块

初始化代码的工作，就是将上个章节生成verilog函数中的命令条条执行，碰到需要等待的地方等待，需要读某个标志位的地方就一直读，直到标志位符合要求。下面贴出初始化代码。

module ad9361_init(
	input 				clk,
	input 				arst,
	output 	reg			read,
	output 	reg			write,
	output 	reg	[9:0]	address,
	output 	reg	[7:0]	writedata,
	input 		[7:0]	readdata,
	input 				waitrequest,
	output	reg			chip_rst_n,
	output 	reg			init_done
);
	//`define MODELSIM
	`define SPI_CLK_FREQ 40 //MHz	
	`include "fdd_600m.v"
	reg		[12:0]	index;
	reg		[2:0]	state;
	reg 	[31:0] 	delay_cnt;
	
	reg [18:0]	command;
	
	always @ (posedge clk)
		command <= fdd_600m(index);
	
	
	always @ (posedge clk or posedge arst)
	begin
		if(arst) begin index<=0;write<=0;read<=0;address<=0;writedata<=0;init_done<=0;state<=0;delay_cnt<=0;chip_rst_n<=0;end
		else begin
			case(state)
				0:begin
					if(delay_cnt<SPI_CLK_FREQ*1000)
						delay_cnt<=delay_cnt+1;
					else begin
						chip_rst_n<=1;
						delay_cnt<=0;
					end
				end
				1:begin {write,address,writedata}<=command;read<=~command[18];state<=1;end
				2:if(~waitrequest) begin write<=0;read<=0;state<=read? 3:4;end
				3:/*此处有省略*/
				4:begin index<=index+1;state<=state+1;end
				5:state<=state+1;
				6:state<=1;
				7:init_done<=1;
				default:state<=0;
			endcase
		end
	end
endmodule

思路：按索引index依次执行上一篇文章中生成的初始化脚本命令。一般的命令执行完后，直接执行下一条，遇到特殊的指令，在状态机state==3时做处理

下一章讲解AD9361的数据接口

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