Verilog刷题笔记10

题目：
You are given a module with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The port needs to be connected to all instances. my_dffclk

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

我的解法：

module top_module ( input clk, input d, output q );
    wire q12;
    wire q23;
    
    my_dff dff1(clk,d,q12);
    my_dff dff2(clk,q12,q23);
    my_dff dff3(clk,q23,q);
endmodule

结果正确：