<2012 12 01> 三星Exynos3110 Cortex-A8 1GHz 处理器 蜂鸟 S5PC110 S5PV210
The Exynos 3110 is optimally designed for use in mobile connected devices such as multimedia intensive Smart Phones and other portable media players. Through the use of a variety of low power design technologies, such as 45nm Low Power fabrication process and intricate low power architectures, the Exynos 3110 achieves significantly longer battery life for mobile devices running on standard size batteries. The Exynos 3110 incorporates 32KB data and 32KB instruction caches, and is equipped with a 512KB L2 cache. With the 1Ghz clock speed and the large size L2 cache, the Exynos 3110 enables real-time applications such as web browsing and dynamic UI to run smoothly and react with a fast response time.
Exynos 3110 is a 32-bit RISC cost-effective, low power, and high performance micro¡þprocessor solution for mobile phones and general applications. It integrates the ARM CortexA8 core, which implements the ARM architecture V7-A with supporting peripherals.
To provide optimized H/W performance for the 3.xG & 4G communication services, Exynos 3110 adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as motion video processing, display control and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG2/4, H.263, and H.264, and decoding of VC1, Xvid. This hardware accelerator (MFC) supports real-time video conferencing and Analog TV out for NTSC/PAL mode and HDMI for HD TV.
Exynos 3110 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ROM external memory ports for parallel access and two dedicated DRAM ports to meet high bandwidths. Each DRAM controller supports LPDDR1 (mobile DDR), LPDDR2, or DDR2. Flash/ROM Port supports NAND Flash, NOR Flash, OneNAND, SRAM and ROM type external memory.
To reduce total system cost and enhance overall functionality, Exynos 3110 includes many hardware peripherals such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, MIPI CSI-2, System Manager for power management, ATA interface, four UARTs, 24-channel DMA, four Timers, General I/O Ports, three IIS, S/PDIF, three IIC-BUS interface, two HS-SPI, four SD Host and high-speed Multimedia Card interface, USB Host 2.0 and USB Device 2.0 operating at high speed (480Mbps) with USB 2.0 PHY respectively, and four PLLs for clock generation. POP (Package on Package) option with MCP is available for small form factor applications.
- ARM CortexA8 based CPU Subsystem with NEON
- 32/32KB I/D Cache, 512KB L2 Cache- 800MHz/1GHz Operating Frequency at 1.2 V and 1.25 V respectively - 64-bit Multi-layer bus architecture
- Advanced power management for mobile applications
- 64KB ROM for secure booting and 96KB RAM for security function
- 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224pixels for scaled and 8192 pixels for un-scaled resolution
- Multi Format CODEC provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30fps and decoding of MPEG2/VC1/Xvid video up to 1080p@30fps
- JPEG codec support up to 80Mpixels/s
- 3D Graphics Acceleration with Programmable Shader up to 20M triangles/s, 1000Mpixels/s
- Dedicated 2D Graphics acceleration supporting BitBLT, Alpha-blending, and Stretch function
- 1/2/4/8 bpp palletized or 8/16/24bpp non-palletized Color-TFT, up to SXGA resolution
- Composite TV-out interface with video amplifier and HDMI 1.3 interface
- 4-lane MIPI-DSI and MIPI-CSI interface
- One AC-97 audio codec interface and three PCMs serial audio interface
- Three 24-bit IISs interface
- One TX only S/PDIF interface support for digital audio
- Three IICs interface support
- Two high speed SPIs
- Four UARTs up to 3Mbps port for Bluetooth 2.0
- On-chip USB 2.0 Device supporting FS/HS (12Mbps/480Mbps, on-chip transceiver)
- On-chip USB 2.0 Host supporting LS/FS/HS (1.5Mbps/12Mbps/480Mbps, on-chip transceiver)
- Asynchronous Modem Interface support including 16KB DPSRAM
- Four SD/SDIO/HS-MMC interface supporting SD Host 2.0, HS-MMC 4.3, SD Card 2.0, SDIO 1.0
- ATA/ATAPI-6 compatible interface support
- 24-channel DMA controller (8 channels for memory-to-memory DMA, 16 channels for Peripheral DMA)
- Support 14×8 key matrix
- 10-channel, 12-bit multiplexed ADC
- Configurable GPIOs
- Real time clock, PLL, timer with PWM and watch dog timer
- Memory Subsystem- Asynchronous SRAM / ROM / NOR Interface with x8 or x16 data bus- NAND interface with x8 data bus- Muxed/Demuxed OneNAND Interface with x16 data bus- LPDDR1 interface with x16 or x32 data bus (266 ~ 400Mbps/pin DDR)- DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR)- LPDDR2 interface (400Mbps/pin DDR)