12m晶振----->pll------>cpu
Mux多路选择器
Div分频器
示例代码如下：
汇编实现
.globlclock_init
clock_init:
/*1.设置LOCK_TIME*/
ldrr0,=0x7E00F000/*APLL_LOCK*/
ldrr1,=0x0000FFFF
strr1,[r0]
strr1,[r0,#4] /*MPLL_LOCK*/
strr1,[r0,#8] /*EPLL_LOCK*/
#defineOTHERS 0x7e00f900
@setasyncmode/*当CPU时钟!=HCLK时，要设为异步模式*/
ldrr0,=OTHERS
ldrr1,[r0]
bicr1,#0xc0
strr1,[r0]
loop1: /*等待，直到CPU进入异步模式*/
ldrr0,=OTHERS
ldrr1,[r0]
andr1,#0xf00
cmpr1,#0
bneloop1
/*SYNC667*/
/*MISC_CON[19]=0*/
#defineARM_RATIO0/*ARMCLK=DOUTAPLL/(ARM_RATIO+1)*/
#defineHCLKX2_RATIO1/*HCLKX2=HCLKX2IN/(HCLKX2_RATIO+1)*/
#defineHCLK_RATIO1/*HCLK=HCLKX2/(HCLK_RATIO+1)*/
#definePCLK_RATIO3/*PCLK=HCLKX2/(PCLK_RATIO+1)*/
#defineMPLL_RATIO0/*DOUTMPLL=MOUTMPLL/(MPLL_RATIO+1)*/
ldrr0,=0x7E00F020/*CLK_DIV0*/
ldrr1,=(ARM_RATIO)|(MPLL_RATIO<<4)|(HCLK_RATIO<<8)|(HCLKX2_RATIO<<9)|(PCLK_RATIO<<12)
strr1,[r0]
/*2.配置时钟*/
/*2.1配置APLL*/
/*2.1.1设置APLL
*2.1.2MUXAPLL
*2.1.3SYNC667
*2.1.4DIVAPLL
*/
#defineAPLL_CON_VAL((1<<31)|(266<<16)|(3<<8)|(1))
ldrr0,=0x7E00F00C
ldrr1,=APLL_CON_VAL
strr1,[r0] /*APLL_CON,FOUTAPL=MDIV*Fin/(PDIV*2^SDIV)=266*12/(3*2^1)=532MHz*/
/*2.2配置MPLL*/
/*2.2.1设置MPLL
*2.2.2MUXMPLL
*2.2.3SYNCMUX
*2.2.4SYNC667
*2.2.5HCLKX2_RATIO
*2.2.6PCLK_RATIO
*/
#defineMPLL_CON_VAL((1<<31)|(266<<16)|(3<<8)|(1))
ldrr0,=0x7E00F010
ldrr1,=MPLL_CON_VAL
strr1,[r0] /*MPLL_CON,FOUTMPL=MDIV*Fin/(PDIV*2^SDIV)=266*12/(3*2^1)=532MHz*/
/*3.选择PLL的输出作为时钟源*/
ldrr0,=0x7E00F01C
ldrr1,=0x03
strr1,[r0]
movpc,lr
C实现
#defineAPLL_LOCK(*((volatileunsignedlong*)0x7E00F000))
#defineMPLL_LOCK(*((volatileunsignedlong*)0x7E00F004))
#defineEPLL_LOCK(*((volatileunsignedlong*)0x7E00F008))
#defineOTHERS (*((volatileunsignedlong*)0x7E00F900))
#defineCLK_DIV0(*((volatileunsignedlong*)0x7E00F020))
#defineARM_RATIO 0
#defineHCLKX2_RATIO 4
#defineHCLK_RATIO 0
#definePCLK_RATIO 1
#defineMPLL_RATIO 0
#defineAPLL_CON(*((volatileunsignedlong*)0x7E00F00C))
#defineAPLL_CON_VAL((1<<31)|(250<<16)|(3<<8)|(1))
#defineMPLL_CON(*((volatileunsignedlong*)0x7E00F010))
#defineMPLL_CON_VAL((1<<31)|(250<<16)|(3<<8)|(1))
#defineCLK_SRC(*((volatileunsignedlong*)0x7E00F01C))
voidclock_init(void){
APLL_LOCK=0XFFFF;
MPLL_LOCK=0XFFFF;
EPLL_LOCK=0XFFFF;
/*当CPU时钟!=HCLK时，要设为异步模式*/
OTHERS&=~0XC0;
while((OTHERS&0XF00)!=0);
CLK_DIV0=(ARM_RATIO)|(MPLL_RATIO<<4)|(HCLK_RATIO<<8)|(HCLKX2_RATIO<<9)|(PCLK_RATIO<<12);
APLL_CON=APLL_CON_VAL;/*500MHZ*/
MPLL_CON=MPLL_CON_VAL;/*500MHZ*/
CLK_SRC=0X03;
}