AHB总线RAM外设SystemVerilog实例

 1 `include "defines.sv"
 2 
 3 module ahb_ram #(
 4     parameter   AW = 16,
 5                 DW = 32
 6 ) (
 7     input   logic               HCLK,
 8     input   logic               HRESETn,
 9     ahb_slv_intf.s              ahb
10 );
11 
12     localparam  BYTE_BITS   = 8,
13                 OFST_BITS   = $clog2(DW/BYTE_BITS),
14                 WORD_NUM    = 2**(AW-OFST_BITS);
15     
16     logic   [AW-1:OFST_BITS]    wr_adr;
17     logic   [AW-1:OFST_BITS]    ram_adr;
18     
19     logic   ram_wr, ram_rd;
20     
21     assign ahb.HREADY = 1'b1;
22     assign ahb.HRESP  = HRESP_OKAY;
23     
24     always_ff @(posedge HCLK or negedge HRESETn) begin
25         if (!HRESETn)
26             wr_adr <= '0;
27         else if (ahb.HSEL && ahb.HREADY)
28             wr_adr <= ahb.HADDR[AW-1:OFST_BITS];
29     end
30 
31     assign ram_adr = ram_wr ? wr_adr : ahb.HADDR[AW-1:OFST_BITS];
32     
33     always_ff @(posedge HCLK or negedge HRESETn) begin
34         if (!HRESETn)
35             ram_wr <= 1'b0;
36         else begin
37             if (ahb.HSEL && (ahb.HTRANS == HTRANS_SEQ || ahb.HTRANS == HTRANS_NONSEQ) && ahb.HWRITE)
38                 ram_wr <= 1'b1;
39             else
40                 ram_wr <= 1'b0;
41         end
42     end
43     
44     always_comb begin
45         if (ahb.HSEL && (ahb.HTRANS == HTRANS_SEQ || ahb.HTRANS == HTRANS_NONSEQ) && !ahb.HWRITE)
46             ram_rd = 1'b1;
47         else
48             ram_rd = 1'b0;
49     end
50 
51     logic   [DW-1:0]    mem[WORD_NUM];
52     
53     
54     initial begin
55         $readmemh("data.txt", mem);
56     end
57     
58     always_ff @(posedge HCLK or negedge HRESETn) begin
59         if (!HRESETn)
60             ahb.HRDATA <= '0;
61         else begin
62             if (ram_wr)
63                 mem[ram_adr]  <= ahb.HWDATA;
64             else if (ram_rd)
65                 ahb.HRDATA <= mem[ram_adr];
66         end
67         else
68             ahb.HRDATA <= '0;
69     end
70 
71 endmodule: ahb_ram