深入理解ARM体系架构（S3C6410）---S3C6410系统时钟

本文由muge0913编写，转载请注明出处：http://blog.csdn.net/muge0913/article/details/7364706

作者张同浩，邮箱:[email protected]

系统时钟控制逻辑，在S3C6410 中生成所需的系统时钟信号，用于CPU 的ARMCLK, 用于AXI/AHB 总线外设的HCLK 和APB 总线外设的PCLK。在S3C6410 中有三个PLL。一个仅用于ARMCLK，一个用于HCLK 和 PCLK，最后一个用于外设，特别用于音频相关的时钟。The third thingis for peripheral, especially for audio related clocks.通过外部提供的时钟源，时钟控制逻辑产生慢速时钟信号ARMCLK,HCLK 和 PCLK。该每个外设块的时钟信号可能被启用或禁用，由软件控制以减少电源消耗。

 

在电源控制逻辑中，S3C6410 有多种电源管理方案，以保持电力系统的最佳消耗。In the power control logic, S3C6410X has various power managementschemes to keep optimal power consumption for a given task. 在S3C6410中，电源管理由四个模块组成：通用时钟门控模式，空闲模式，停止模式和睡眠模式。

 

1、在S3C6410中，通用时钟门控模式用来控制内部外设时钟的开/关。可以通过用于外设所要求的特定应用提供时钟，使用通用时钟门控模式来优化S3C6410的电源消耗。例如：如果定时器没有要求，则可以中断时钟定时器，以降低功耗。General Clock Gating mode is used to control the ON/OFF of clocksfor internal peripherals in S3C6410X. You can optimize the power consumption ofS3C6410X using this General Clock Gating mode by supplying clocks for peripheralsthat are required for a certain application. For example, if a timer is notrequired, then you can disconnect the clock to the timer to reduce power.

2、闲置模式仅中断ARMCLK到CPU 内核，它提供时钟给所有外设。通过使用闲置模式，电力消耗通过CPU

内核而减少。

3、停止模式通过禁用PLL冻结所有时钟到CPU 以及外设。在S3C6410 中，电力消耗仅因为漏电流。

4、睡眠模式断开内部电源。因此，除了唤醒逻辑单元消耗的电量，CPU和内部逻辑消耗电量将为零。为了使用睡眠模式，两个独立的电源是必需的。其中一个电源为唤醒逻辑提供电力，另一个提供其他内部逻辑，包括CPU。SLEEP mode disconnects the internal power.Therefore, the power consumption due to CPU and the internal logic except thewakeup logic will be zero. In order to use the SLEEP mode two independent powersources are required. One of the two power sources supplies the power for thewake-up logic. The other one supplies the other internal logic including CPU,and must be controlled in order to be turned ON/OFF. In SLEEP mode, the secondpower supply source for the CPU and internal logic will be turned off.

 

 

3.1 系统控制器的特性

The System Controller includes the following features:

• Three PLLs: ARM PLL, main PLL, extra PLL (for the modules those usespecial frequency)

• Five power-saving mode: NORMAL, IDLE, STOP, DEEP-STOP, and SLEEP

• Six controllable power domain: domain-G, domain-V, domain-I,domain-P, domain-F, domain-S

• Control operating clocks of internal sub-blocks

• Control bus priority

 

3.2 功能描述

这部分主要介绍S3C6410 系统控制器的功能。包含时钟的体系结构，复位设计和电源管理模式。

1、 硬件结构

S3C6410是由ARM1176核、一些多媒体协处理器（co-processors）、多种外设IPs组成。ARM1176核是通过64位AXI总线与存储控制器相连的，这样做是为了满足带宽的需要。多媒体协处理（MFC多格式编码器、JPEG、camera接口、TV译码器、3D加速器等）器被分为五个电源域，这五个电源域可被单独控制以降低功耗。S3C6410X consists of ARM1176 processor, several media and graphicco-processors and various peripheral IPs. ARM1176 processor is connected toseveral memory controllers through 64-bit AXI-bus. This is done to meetbandwidth requirements. Media and graphic coprocessors, which include MFC(Multi-Format Codec), JPEG, Camera interface, TV encoder, 3D accelerator and etc,are divided into six power domains. The six power domain can be controlledindependently to reduce unwanted power consumption when the IPs is not requiredfor an application program.

2、时钟结构

时钟源在外部晶振和外部时钟二者之间进行选择。时钟发生器由三个PLL组成，最高可产生1.6GHz的信号。

3.时钟源的选择

The OM[4:0] pins determines theoperating mode of S3C6410X when the external reset signal is asserted. Asdescribed in the table, the OM[0] selects the external clock source, i.e., ifthe OM[0] is 0, the XXTIpll (external crystal) is selected.

Otherwise, XEXTCLK is selected.

The operating mode is mainlyclassified into six categories according to the boot device. The boot devicecan be among SROM, NOR, OneNAND, MODEM and Internal ROM. When NAND Flash deviceis used, XSELNAND pin must be 1, even if it is used as boot device or storagedevice. When OneNAND Flash device is used, XSELNAND must be 0, even if it isused as boot device or storage device. When NAND/OneNAND device is not used,

XSELNAND can be 0 or 1.

4、锁相环

Clock selection betweenPLLs and input reference clock

Figure 3-4illustrates the clock generation logic. S3C6410X has three PLLs which are APLLfor ARM operating clock, MPLL for main operating clock, and EPLL for specialpurpose. The operating clocks are divided into three groups. The first thing isARM clock, which is generated from APLL. MPLL generates the main system clocks,which are used for operating AXI, AHB, and APB bus operation. The last group isgenerated from EPLL. Mainly, the generated clocks are used for peripheral IPs,i.e., UART, IIS, IIC, and etc. The lowest three bits of CLK_SRC registercontrol the source clocks of three groups. When the bit has 0, then the inputclock is bypassed to the group. Otherwise, the PLL output will be applied tothe group.

1)ARM和AXI/AHB/APB时钟

ARM1176最大支持667MHZ，在不改变PLL的情况下，可以通过DIVarm来控制该频率。

S3C6410由AXI、AHB、APB总线组成。IPs可以连接相应总线来满足I/O带宽和操作性能。连接在AXI/AHB的总线上的设备，最高可以达到133MHz的速度。当连接在APB总线上时，最高可以达到66MHz的速度。总线速度很高程度上依赖于AHB和APB总线之间的同步数据传输。

ARM and AXI/AHB/APB bus clock generation

ARM1176 processor of S3C6410X runs up to maximum 667MHz. Theoperating frequency can be controlled by the internal clock divider, DIVARM,without changing PLL frequency. The divider ratio varies from 1 to 16. ARM processordecreases the operating speed to reduce power dissipation.S3C6410X consists ofAXI bus, AHB bus, and APB bus to optimize the performance requirements.Internal IPs are connected to appropriate bus systems to meet their I/Obandwidth and operating performance. When they are attached to AXI bus or AHBbus, the operating speed can be up to maximum 133MHz. While they are attachedto APB bus, the maximum operating speed can be up to 66MHz. Moreover, the busspeed between AHB and APB has high dependency to synchronize data transmission.Figure 3-5 illustrates the part of bus clock generation to meet therequirements of bus system clocks.

HCLKx2用于两个DDR控制器，DDR0、DDR1，最高可达到266MHZ，每个DDR控制器可以单独控制，以用来降低功耗。所有的AHB总线上的时钟是由DIVhclk分频得来的，同样，也可以单独控制来降低功耗。HCLK_GATE寄存器来配置HCLKx2和HCLK。

 

APB总线与AHB总线类似，但是注意：在AHB和APB总线之间的频率比必须隔着一个偶数值，例如：如果DIVhclk是1，那么DIVpclk必须是1、3…..，否则，则不能传输数据。

Low-speed interconnection IPs transfer data through APB bus system.APB clocks of them are running at up to 66MHz as described in the above sectionand generated from DIVPCLK clock divider. They are also masked using PCLK_GATEregister. As described, the frequency ratio between AHB clock and APB clockmust be an even integer value. For example, if DIVHCLK has 1 of CLK_DIV0[8],then DIVPCLK must be 1, 3, ... of CLK_DIV0[15:12].Otherwise, the IPs on APB bussystem cannot transfer data correctly.

 

在AHB总线上的JPEG和安全子系统不能运行在133MHz。AHB总线用DIVjpeg和DIVsecur为它们单独产生时钟信号，因此它们与APB之间的频率也要隔着一个偶数。

APLL单独用于ARM核，其值不作约束。

其他时钟，用的时候查看手册即可。

2)MFC时钟

3)camera　I/F(接口)时钟

4)显示时钟（POST、LCD和scaler

5)音频时钟（IIS和PCM）

6)UART、SPI、MMC时钟

7)IrDA　和USBHOST时钟

8)时钟的开关控制

可以通过控制HCLK_GATE、PCLK_GATE、SCLK_GATE。

9)时钟的输出

有一个时钟输出端口，产生内部时钟，用于中断或调试。