“知其然,还要知其所以然”,在搭建好ORPSoC的仿真环境和调试环境之后,我们有必要对仿真和调试系统中扮演重要角色的jtag_tap模块和adv_dbg_if模块进行进一步的分析,以了解其工作机制。
本小节就来分析advanced debug system中的tap_top模块。
在分析JTAG的具体实现之前,我们先了解一下JTAGF的基本知识。
// Define IDCODE Value `define IDCODE_VALUE 32'h149511c3 // 0001 version // 0100100101010001 part number (IQ) // 00011100001 manufacturer id (flextronics) // 1 required by standard // Length of the Instruction register `define IR_LENGTH 4 // Supported Instructions `define EXTEST 4'b0000 `define SAMPLE_PRELOAD 4'b0001 `define IDCODE 4'b0010 `define DEBUG 4'b1000 `define MBIST 4'b1001 `define BYPASS 4'b1111
-- This is a minimal BSDL file describing the particulars -- of the OpenCores standard / native TAP. It is designed -- only to be used by the adv_jtag_bridge program. This -- file almost certainly lacks key entries and attributes -- required by other JTAG / BSDL systems. -- -- by Nathan Yawn ([email protected]) -- Copyright: This file is released into the public domain. -- entity OC_TAP is attribute INSTRUCTION_LENGTH of OC_TAP : entity is 4; attribute INSTRUCTION_OPCODE of OC_TAP : entity is "EXTEST (0000)," & "SAMPLE_PRELOAD (0001)," & "IDCODE (0010)," & "MBIST (1001)," & "DEBUG (1000)," & "BYPASS (1111),"; attribute IDCODE_REGISTER of OC_TAP : entity is "0001" & -- version "0100100101010001" & -- part number "00011100001" & -- manufacturer (flextronics) "1"; -- required by 1149.1 end OC_TAP;
// Top module module tap_top( // JTAG pads tms_pad_i, tck_pad_i, trstn_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o, // TAP states test_logic_reset_o, run_test_idle_o, shift_dr_o, pause_dr_o, update_dr_o, capture_dr_o, // Select signals for boundary scan or mbist extest_select_o, sample_preload_select_o, mbist_select_o, debug_select_o, // TDO signal that is connected to TDI of sub-modules. tdi_o, // TDI signals from sub-modules debug_tdo_i, // from debug module bs_chain_tdo_i, // from Boundary Scan Chain mbist_tdo_i // from Mbist Chain );
/********************************************************************************** * * * Selecting active data register * * * **********************************************************************************/ always @ (latched_jtag_ir) begin extest_select = 1'b0; sample_preload_select = 1'b0; idcode_select = 1'b0; mbist_select = 1'b0; debug_select = 1'b0; bypass_select = 1'b0; case(latched_jtag_ir) /* synthesis parallel_case */ `EXTEST: extest_select = 1'b1; // External test `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload `IDCODE: idcode_select = 1'b1; // ID Code `MBIST: mbist_select = 1'b1; // Mbist test `DEBUG: debug_select = 1'b1; // Debug `BYPASS: bypass_select = 1'b1; // BYPASS default: bypass_select = 1'b1; // BYPASS endcase end
/********************************************************************************** * * * TAP State Machine: Fully JTAG compliant * * * **********************************************************************************/ // Definition of machine state values. We could one-hot encode this, and use 16 // registers, but this uses binary encoding for the minimum of 4 DFF's instead. `define STATE_test_logic_reset 4'hF `define STATE_run_test_idle 4'hC `define STATE_select_dr_scan 4'h7 `define STATE_capture_dr 4'h6 `define STATE_shift_dr 4'h2 `define STATE_exit1_dr 4'h1 `define STATE_pause_dr 4'h3 `define STATE_exit2_dr 4'h0 `define STATE_update_dr 4'h5 `define STATE_select_ir_scan 4'h4 `define STATE_capture_ir 4'hE `define STATE_shift_ir 4'hA `define STATE_exit1_ir 4'h9 `define STATE_pause_ir 4'hB `define STATE_exit2_ir 4'h8 `define STATE_update_ir 4'hD reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal // sequential part of the FSM always @ (posedge tck_pad_i or negedge trstn_pad_i) begin if(trstn_pad_i == 0) TAP_state = `STATE_test_logic_reset; else TAP_state = next_TAP_state; end // Determination of next state; purely combinatorial always @ (TAP_state or tms_pad_i) begin case(TAP_state) `STATE_test_logic_reset: begin if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; else next_TAP_state = `STATE_run_test_idle; end `STATE_run_test_idle: begin if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; else next_TAP_state = `STATE_run_test_idle; end `STATE_select_dr_scan: begin if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan; else next_TAP_state = `STATE_capture_dr; end `STATE_capture_dr: begin if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; else next_TAP_state = `STATE_shift_dr; end `STATE_shift_dr: begin if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; else next_TAP_state = `STATE_shift_dr; end `STATE_exit1_dr: begin if(tms_pad_i) next_TAP_state = `STATE_update_dr; else next_TAP_state = `STATE_pause_dr; end `STATE_pause_dr: begin if(tms_pad_i) next_TAP_state = `STATE_exit2_dr; else next_TAP_state = `STATE_pause_dr; end `STATE_exit2_dr: begin if(tms_pad_i) next_TAP_state = `STATE_update_dr; else next_TAP_state = `STATE_shift_dr; end `STATE_update_dr: begin if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; else next_TAP_state = `STATE_run_test_idle; end `STATE_select_ir_scan: begin if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; else next_TAP_state = `STATE_capture_ir; end `STATE_capture_ir: begin if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; else next_TAP_state = `STATE_shift_ir; end `STATE_shift_ir: begin if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; else next_TAP_state = `STATE_shift_ir; end `STATE_exit1_ir: begin if(tms_pad_i) next_TAP_state = `STATE_update_ir; else next_TAP_state = `STATE_pause_ir; end `STATE_pause_ir: begin if(tms_pad_i) next_TAP_state = `STATE_exit2_ir; else next_TAP_state = `STATE_pause_ir; end `STATE_exit2_ir: begin if(tms_pad_i) next_TAP_state = `STATE_update_ir; else next_TAP_state = `STATE_shift_ir; end `STATE_update_ir: begin if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; else next_TAP_state = `STATE_run_test_idle; end default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen endcase end // Outputs of state machine, pure combinatorial always @ (TAP_state) begin // Default everything to 0, keeps the case statement simple test_logic_reset = 1'b0; run_test_idle = 1'b0; select_dr_scan = 1'b0; capture_dr = 1'b0; shift_dr = 1'b0; exit1_dr = 1'b0; pause_dr = 1'b0; exit2_dr = 1'b0; update_dr = 1'b0; select_ir_scan = 1'b0; capture_ir = 1'b0; shift_ir = 1'b0; exit1_ir = 1'b0; pause_ir = 1'b0; exit2_ir = 1'b0; update_ir = 1'b0; case(TAP_state) `STATE_test_logic_reset: test_logic_reset = 1'b1; `STATE_run_test_idle: run_test_idle = 1'b1; `STATE_select_dr_scan: select_dr_scan = 1'b1; `STATE_capture_dr: capture_dr = 1'b1; `STATE_shift_dr: shift_dr = 1'b1; `STATE_exit1_dr: exit1_dr = 1'b1; `STATE_pause_dr: pause_dr = 1'b1; `STATE_exit2_dr: exit2_dr = 1'b1; `STATE_update_dr: update_dr = 1'b1; `STATE_select_ir_scan: select_ir_scan = 1'b1; `STATE_capture_ir: capture_ir = 1'b1; `STATE_shift_ir: shift_ir = 1'b1; `STATE_exit1_ir: exit1_ir = 1'b1; `STATE_pause_ir: pause_ir = 1'b1; `STATE_exit2_ir: exit2_ir = 1'b1; `STATE_update_ir: update_ir = 1'b1; default: ; endcase end /********************************************************************************** * * * End: TAP State Machine * * * **********************************************************************************/
/********************************************************************************** * * * jtag_ir: JTAG Instruction Register * * * **********************************************************************************/ reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg; wire instruction_tdo; always @ (posedge tck_pad_i or negedge trstn_pad_i) begin if(trstn_pad_i == 0) jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0; else if (test_logic_reset == 1) jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0; else if(capture_ir) jtag_ir <= 4'b0101; // This value is fixed for easier fault detection else if(shift_ir) jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]}; end assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX // Updating jtag_ir (Instruction Register) // jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1 always @ (negedge tck_pad_i or negedge trstn_pad_i) begin if(trstn_pad_i == 0) latched_jtag_ir <= `IDCODE; // IDCODE selected after reset else if (test_logic_reset) latched_jtag_ir <= `IDCODE; // IDCODE selected after reset else if(update_ir) latched_jtag_ir <= jtag_ir; end /********************************************************************************** * * * End: jtag_ir * * * **********************************************************************************/
/********************************************************************************** * * * idcode logic * * * **********************************************************************************/ reg [31:0] idcode_reg; wire idcode_tdo; always @ (posedge tck_pad_i or negedge trstn_pad_i) begin if(trstn_pad_i == 0) idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset else if (test_logic_reset) idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset else if(idcode_select & capture_dr) idcode_reg <= `IDCODE_VALUE; else if(idcode_select & shift_dr) idcode_reg <= {tdi_pad_i, idcode_reg[31:1]}; end assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX /********************************************************************************** * * * End: idcode logic * * * **********************************************************************************/
/********************************************************************************** * * * Bypass logic * * * **********************************************************************************/ wire bypassed_tdo; reg bypass_reg; // This is a 1-bit register always @ (posedge tck_pad_i or negedge trstn_pad_i) begin if (trstn_pad_i == 0) bypass_reg <= 1'b0; else if (test_logic_reset == 1) bypass_reg <= 1'b0; else if (bypass_select & capture_dr) bypass_reg<= 1'b0; else if(bypass_select & shift_dr) bypass_reg<= tdi_pad_i; end assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX /********************************************************************************** * * * End: Bypass logic * * * **********************************************************************************/
/********************************************************************************** * * * Multiplexing TDO data * * * **********************************************************************************/ reg tdo_mux_out; // really just a wire always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or bs_chain_tdo_i) begin if(shift_ir) tdo_mux_out = instruction_tdo; else begin case(latched_jtag_ir) // synthesis parallel_case `IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code `DEBUG: tdo_mux_out = debug_tdo_i; // Debug `SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading `EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test `MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test default: tdo_mux_out = bypassed_tdo; // BYPASS instruction endcase end end // TDO changes state at negative edge of TCK always @ (negedge tck_pad_i) begin tdo_pad_o = tdo_mux_out; end // Tristate control for tdo_pad_o pin always @ (posedge tck_pad_i) begin tdo_padoe_o <= shift_ir | shift_dr; end /********************************************************************************** * * * End: Multiplexing TDO data * * * **********************************************************************************/
////////////////////////////////////////////////////////////////////// // Functions which operate on the JTAG TAP /* Resets JTAG - Writes TRST=1, and TRST=0. Sends 8 TMS to put the TAP * in test_logic_reset mode, for good measure. */ int tap_reset(void) { int i; int err = APP_ERR_NONE; debug("\nreset("); err |= jtag_write_bit(0); JTAG_RETRY_WAIT(); /* In case we don't have TRST reset it manually */ for(i = 0; i < 8; i++) err |= jtag_write_bit(TMS); err |= jtag_write_bit(TRST); // if TRST not supported, this puts us in test logic/reset JTAG_RETRY_WAIT(); err |= jtag_write_bit(0); // run test / idle debug(")\n"); // Reset data on current module/register selections current_chain = -1; // (this is only for the adv. debug i/f...bit of a kludge) for(i = 0; i < DBG_MAX_MODULES; i++) current_reg_idx[i] = -1; return err; } // Set the IR with the DEBUG command, one way or the other int tap_enable_debug_module(void) { uint32_t data; int err = APP_ERR_NONE; if(global_altera_virtual_jtag) { /* Set for virtual IR shift */ err |= tap_set_ir(vjtag_cmd_vir); // This is the altera virtual IR scan command err |= jtag_write_bit(TMS); /* SELECT_DR SCAN */ err |= jtag_write_bit(0); /* CAPTURE_DR */ err |= jtag_write_bit(0); /* SHIFT_DR */ /* Select debug scan chain in virtual IR */ data = (0x1<<ALT_VJTAG_IR_SIZE)|ALT_VJTAG_CMD_DEBUG; err |= jtag_write_stream(&data, (ALT_VJTAG_IR_SIZE+1), 1); // EXIT1_DR err |= jtag_write_bit(TMS); /* UPDATE_DR */ err |= jtag_write_bit(0); /* IDLE */ // This is a command to set an altera device to the "virtual DR shift" command err |= tap_set_ir(vjtag_cmd_vdr); } else { /* select debug scan chain and stay in it forever */ err |= tap_set_ir(global_jtag_cmd_debug); } return err; } /* Moves a value into the TAP instruction register (IR) * Includes adjustment for scan chain IR length. */ uint32_t *ir_chain = NULL; int tap_set_ir(int ir) { int chain_size; int chain_size_words; int i; int startoffset, startshift; int err = APP_ERR_NONE; // Adjust desired IR with prefix, postfix bits to set other devices in the chain to BYPASS chain_size = global_IR_size + global_IR_prefix_bits + global_IR_postfix_bits; chain_size_words = (chain_size/32)+1; if(ir_chain == NULL) { // We have no way to know in advance how many bits there are in the combined IR register ir_chain = (uint32_t *) malloc(chain_size_words * sizeof(uint32_t)); if(ir_chain == NULL) return APP_ERR_MALLOC; } for(i = 0; i < chain_size_words; i++) ir_chain[i] = 0xFFFFFFFF; // Set all other devices to BYPASS // Copy the IR value into the output stream startoffset = global_IR_postfix_bits/32; startshift = (global_IR_postfix_bits - (startoffset*32)); ir_chain[startoffset] &= (ir << startshift); ir_chain[startoffset] |= ~(0xFFFFFFFF << startshift); // Put the 1's back in the LSB positions ir_chain[startoffset] |= (0xFFFFFFFF << (startshift + global_IR_size)); // Put 1's back in MSB positions, if any if((startshift + global_IR_size) > 32) { // Deal with spill into the next word ir_chain[startoffset+1] &= ir >> (32-startshift); ir_chain[startoffset+1] |= (0xFFFFFFFF << (global_IR_size - (32-startshift))); // Put the 1's back in the MSB positions } // Do the actual JTAG transaction debug("Set IR 0x%X\n", ir); err |= jtag_write_bit(TMS); /* SELECT_DR SCAN */ err |= jtag_write_bit(TMS); /* SELECT_IR SCAN */ err |= jtag_write_bit(0); /* CAPTURE_IR */ err |= jtag_write_bit(0); /* SHIFT_IR */ /* write data, EXIT1_IR */ debug("Setting IR, size %i, IR_size = %i, pre_size = %i, post_size = %i, data 0x%X\n", chain_size, global_IR_size, global_IR_prefix_bits, global_IR_postfix_bits, ir); err |= cable_write_stream(ir_chain, chain_size, 1); // Use cable_ call directly (not jtag_), so we don't add DR prefix bits debug("Done setting IR\n"); err |= jtag_write_bit(TMS); /* UPDATE_IR */ err |= jtag_write_bit(0); /* IDLE */ current_chain = -1; return err; } // This assumes we are in the IDLE state, and we want to be in the SHIFT_DR state. int tap_set_shift_dr(void) { int err = APP_ERR_NONE; err |= jtag_write_bit(TMS); /* SELECT_DR SCAN */ err |= jtag_write_bit(0); /* CAPTURE_DR */ err |= jtag_write_bit(0); /* SHIFT_DR */ return err; } // This transitions from EXIT1 to IDLE. It should be the last thing called // in any debug unit transaction. int tap_exit_to_idle(void) { int err = APP_ERR_NONE; err |= jtag_write_bit(TMS); /* UPDATE_DR */ err |= jtag_write_bit(0); /* IDLE */ return err; } //////////////////////////////////////////////////////////////////// // Operations to read / write data over JTAG /* Writes TCLK=0, TRST=1, TMS=bit1, TDI=bit0 and TCLK=1, TRST=1, TMS=bit1, TDI=bit0 */ int jtag_write_bit(uint8_t packet) { debug("Wbit(%i)\n", packet); return cable_write_bit(packet); } int jtag_read_write_bit(uint8_t packet, uint8_t *in_bit) { int retval = cable_read_write_bit(packet, in_bit); debug("RWbit(%i,%i)", packet, *in_bit); return retval; } // This automatically adjusts for the DR length (other devices on scan chain) // when the set_TMS flag is true. int jtag_write_stream(uint32_t *out_data, int length_bits, unsigned char set_TMS) { int i; int err = APP_ERR_NONE; if(!set_TMS) err |= cable_write_stream(out_data, length_bits, 0); else if(global_DR_prefix_bits == 0) err |= cable_write_stream(out_data, length_bits, 1); else { err |= cable_write_stream(out_data, length_bits, 0); // It could be faster to do a cable_write_stream for all the prefix bits (if >= 8 bits), // but we'd need a data array of unknown (and theoretically unlimited) // size to hold the 0 bits to write. TODO: alloc/realloc one. for(i = 0; i < (global_DR_prefix_bits-1); i++) err |= jtag_write_bit(0); err |= jtag_write_bit(TMS); } return err; } // When set_TMS is true, this function insures the written data is in the desired position (past prefix bits) // before sending TMS. When 'adjust' is true, this function insures that the data read in accounts for postfix // bits (they are shifted through before the read starts). int jtag_read_write_stream(uint32_t *out_data, uint32_t *in_data, int length_bits, unsigned char adjust, unsigned char set_TMS) { int i; int err = APP_ERR_NONE; if(adjust && (global_DR_postfix_bits > 0)) { // It would be faster to do a cable_write_stream for all the postfix bits, // but we'd need a data array of unknown (and theoretically unlimited) // size to hold the '0' bits to write. for(i = 0; i < global_DR_postfix_bits; i++) err |= cable_write_bit(0); } // If there are both prefix and postfix bits, we may shift more bits than strictly necessary. // If we shifted out the data while burning through the postfix bits, these shifts could be subtracted // from the number of prefix shifts. However, that way leads to madness. if(!set_TMS) err |= cable_read_write_stream(out_data, in_data, length_bits, 0); else if(global_DR_prefix_bits == 0) err |= cable_read_write_stream(out_data, in_data, length_bits, 1); else { err |= cable_read_write_stream(out_data, in_data, length_bits, 0); // It would be faster to do a cable_write_stream for all the prefix bits, // but we'd need a data array of unknown (and theoretically unlimited) // size to hold the '0' bits to write. for(i = 0; i < (global_DR_prefix_bits-1); i++) err |= jtag_write_bit(0); err |= jtag_write_bit(TMS); } return err; } // This function attempts to determine the structure of the JTAG chain // It can determine how many devices are present. // If the devices support the IDCODE command, it will be read and stored. // There is no way to automatically determine the length of the IR registers - // this must be read from a BSDL file, if IDCODE is supported. // When IDCODE is not supported, IR length of the target device must be entered on the command line. #define ALLOC_SIZE 64 #define MAX_DEVICES 1024 int jtag_enumerate_chain(uint32_t **id_array, int *num_devices) { uint32_t invalid_code = 0x7f; // Shift this out, we know we're done when we get it back const unsigned int done_code = 0x3f; // invalid_code is altered, we keep this for comparison (minus the start bit) int devindex = 0; // which device we are currently trying to detect uint32_t tempID; uint32_t temp_manuf_code; uint32_t temp_rest_code; uint8_t start_bit = 0; uint32_t *idcodes; int reallocs = 0; int err = APP_ERR_NONE; // Malloc a reasonable number of entries, we'll expand if we must. Linked lists are overrated. idcodes = (uint32_t *) malloc(ALLOC_SIZE*sizeof(uint32_t)); if(idcodes == NULL) { printf("Failed to allocate memory for device ID codes!\n"); return APP_ERR_MALLOC; } // Put in SHIFT-DR mode err |= jtag_write_bit(TMS); /* SELECT_DR SCAN */ err |= jtag_write_bit(0); /* CAPTURE_DR */ err |= jtag_write_bit(0); /* SHIFT_DR */ printf("Enumerating JTAG chain...\n"); // Putting a limit on the # of devices supported has the useful side effect // of insuring we still exit in error cases (we never get the 0x7f manuf. id) while(devindex < MAX_DEVICES) { // get 1 bit. 0 = BYPASS, 1 = start of IDCODE err |= jtag_read_write_bit(invalid_code&0x01, &start_bit); invalid_code >>= 1; if(start_bit == 0) { if(devindex >= (ALLOC_SIZE << reallocs)) { // Enlarge the memory array if necessary, double the size each time idcodes = (uint32_t *) realloc(idcodes, (ALLOC_SIZE << ++reallocs)*sizeof(uint32_t)); if(idcodes == NULL) { printf("Failed to allocate memory for device ID codes during enumeration!\n"); return APP_ERR_MALLOC; } } idcodes[devindex] = -1; devindex++; } else { // get 11 bit manufacturer code err |= jtag_read_write_stream(&invalid_code, &temp_manuf_code, 11, 0, 0); invalid_code >>= 11; if(temp_manuf_code != done_code) { // get 20 more bits, rest of ID err |= jtag_read_write_stream(&invalid_code, &temp_rest_code, 20, 0, 0); invalid_code >>= 20; tempID = (temp_rest_code << 12) | (temp_manuf_code << 1) | 0x01; if(devindex >= (ALLOC_SIZE << reallocs)) { // Enlarge the memory array if necessary, double the size each time idcodes = (uint32_t *) realloc(idcodes, (ALLOC_SIZE << ++reallocs)*sizeof(unsigned long)); if(idcodes == NULL) { printf("Failed to allocate memory for device ID codes during enumeration!\n"); return APP_ERR_MALLOC; } } idcodes[devindex] = tempID; devindex++; } else { break; } } if(err) // Don't try to keep probing if we get a comm. error return err; } if(devindex >= MAX_DEVICES) printf("WARNING: maximum supported devices on JTAG chain (%i) exceeded.\n", MAX_DEVICES); // Put in IDLE mode err |= jtag_write_bit(TMS); /* EXIT1_DR */ err |= jtag_write_bit(TMS); /* UPDATE_DR */ err |= jtag_write_bit(0); /* IDLE */ *id_array = idcodes; *num_devices = devindex; return err; } int jtag_get_idcode(uint32_t cmd, uint32_t *idcode) { uint32_t data_out = 0; int err = APP_ERR_NONE; unsigned char saveconfig = global_altera_virtual_jtag; global_altera_virtual_jtag = 0; // We want the actual IDCODE, not the virtual device IDCODE err |= tap_set_ir(cmd); err |= tap_set_shift_dr(); err |= jtag_read_write_stream(&data_out, idcode, 32, 1, 1); /* EXIT1_DR */ if(err) printf("Error getting ID code!\n"); // Put in IDLE mode err |= jtag_write_bit(TMS); /* UPDATE_DR */ err |= jtag_write_bit(0); /* IDLE */ global_altera_virtual_jtag = saveconfig; return err; } ///////////////////////////////////////////////////////////////// // Helper functions /* counts retries and returns zero if we should abort */ /* TODO: dynamically adjust timings */ int retry_do() { int err = APP_ERR_NONE; if (soft_retry_no >= NUM_SOFT_RETRIES) { return 0; // *** TODO: Add a 'hard retry', which re-initializes the cable, re-enumerates the bus, etc. } else { /* quick reset */ if(err |= tap_reset()) { printf("Error %s while resetting for retry.\n", get_err_string(err)); return 0; } // Put us back into DEBUG mode if(err |= tap_enable_debug_module()) { printf("Error %s enabling debug module during retry.\n", get_err_string(err)); return 0; } soft_retry_no++; printf("Retry...\n"); } return 1; }