FPGA速度等级问题（Speed Grade）

 

===============================

FPGA的速度等级（speed grade）（1）

XILINX公司FPGASpartan 3E系列XC3S500E速度等级为4.但一直不知道是什么意思.

通过学习知道,

(1)CPLD与FPGA的速度等级定义的区别

(2)不同的公司FPGA的速度等级

(3)同一个公司的不同时期的定义也是不一样的,如XLINX公司

具体内容可以参考以下材料.也可以在GOOGLE里输入 FPGA SPEED GRADE

(4)对于xilinx公司的FPGA的速度等级定义，个人观点：它不是以前所定义的其内部的一些逻辑单元信号传播所花的时间，而是一类内部逻辑器件的运行速度，这些逻辑器件运行时满足一定要求的时钟频率．它没有具体的物理的数据意义，只是一类内部逻辑器件的运行速度的的代号．

 

There is no consistent definition of a speed grade for all devices. Even for Xilinx,

speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

what is the valve of standard grade(FPGA)

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

 

Determining the speed grade of Xilinx devices

Q:

I am having some trouble understanding the numbering system Xilinx uses for speed grade. Could someone explain what the numbers are and how to tell which speed grade is installed on my XS40. FWIW I have an XC4010XL FPGA. The available speed grade choices are -1, -2 -3, or -09.

A:

You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see " 3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.)

For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay.

The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster.

Reference : http://www.xess.com/faq/M0000236.HTM

转自：http://blog.sina.com.cn/s/blog_5e9a27140100c742.html

=====================================================================================================

FPGA的速度等级（speed grade）（2）

Question:

From: vlsigeek
Date Posted : 12/11/2004 4:42:49 AM Hi guys,

What is the speed grade in FPGA. What it tells actually.

Thanks in advance,

Soundar

Comments:

From: vlsi_giant
Posted : 12/27/2004 12:54:29 AM Hi
It is actually the min I/O delay for that device.
Ex: for altera MAX device EPM7128... -15
this -15 indicates this device has min of 15 ns. i/o delay.

yogesh

 

ASIC FPGA VHDL VERILOG CMOS SEMICONDUCTORS MICROPROCESSOR PLACE AND ROUTE MIXED SIGNAL MISCELLANEOUS POST A QUESTION SIGN UP LOGIN CHANGE PASSWORD

speed grade Category: FPGA Question: From: surekha29 Date Posted : 7/19/2006 5:19:41 AM While using xilinx synthesis tool, in the synthesis reports I found a term called speed grade : -6, what does this actually mean?? Comments: From: muthu_kumar Posted : 7/20/2006 12:53:49 AM Hi, Use this field to test a speed grade with your design. Changing the speed grade helps determine a need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints. Select a speed grade from the pull-down list, which contains the available speed grades for the target device. Changing the speed grade in the Options tab tests it with the design; it does not change the speed grade in your FPGA design file. regards muthukumar.p From: vikas Posted : 7/27/2006 6:06:01 AM THE FREQUENCY OF DESIGN DEPENDS UPON SELECTED DEVICESPEED GRADE. suppose u have design that is working on 50 mhz,with a device whose speed grade is 6. now if u want to work at 70 Mhz frequency.and with speed grade 6 u r not acheving that much frequency with that device.then if u take same device with more speed grade then this its sure that ur design fequncy will also increase but it is more costly then then the earlier. if still have any doubt ask dont hesitate [email protected] vikas lakhanpal engineer vlsi designs coral telecom From: vikas Posted : 7/27/2006 6:07:11 AM i think that is the importance of speed grade. From: vikas Posted : 7/27/2006 6:07:13 AM i think that is the importance of speed grade. From: surekha29 Posted : 7/28/2006 2:20:34 AM Thanks for ur comments Muthu Kumar and Vikas. In my search I have found my answer, n thought of sharing... Internal frequency is the speed at which CPLDs/FPGAs can perform operations or transfer data internally. The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. Speed grade indicates the delay in nanoseconds (ns) through a macrocell in the device. For example, a device with a speed grade of –10 has a delay of 10 ns through a macrocell. Devices with low speed grade numbers run faster than devices with high-speed grade numbers. speed grade of -09 implies a delay of 0.9ns. From: muthu_kumar Posted : 7/30/2006 11:23:51 PM Hi surekha,Where u get these ideas?provide the source. i have doubt about your answers.myself and vikas going into the same direction i.e when the device speed grade is increase then the speed of the device also increase.but your answer is different.I warm welcome to all the readers.pls share your points about this question. regards muthukumar.p From: surekha29 Posted : 7/31/2006 2:12:06 AM Hello, I have seen the details at the following links. http://cpld.globalspec.com/ http://www.altera.com/products/devices/dev-format.html http://cpld.globalspec.com/LearnMore/Semiconductors/Programmable_Logic_Devices/CPLD I hope the definition of speed grade for FPGA and CPLD are the same. I think the minus indicates the samething, i.e., as the delay increases the speed(frequency) reduces. From: muthu_kumar Posted : 7/31/2006 11:44:50 PM Hi thanks ,to day i got the new idea from u. xilinx fpga point of view -7 speed grade device faster than -6 speed grade device. But altera cpld point of view -10 speed grade device slower than -9 speed grade device. ok -10 and -9 are denotes the macrocell propagation delay. but if u know any specification of -7 or -6 in FPGA.Anybody knows pls let me know. regards muthukumar.p From: gargji Posted : 8/2/2006 4:58:03 AM Hi Muthu, I can give you some more clearification about FPGA speed grades. In an FPGA the fabricator devides the devices in to some categories. Speed grade -7 means that there is a range of macrocell delay in FPGA which is kept in this category. But in cplds -10 means the macrocell delay is 10 ns. Hope the same is helpfull. rgds From: manish. Posted : 9/2/2006 5:15:56 PM surekha n all comment after checking this site http://www.xess.com/faq/M0000236.HTM From: gauravkshri Posted : 11/9/2006 1:14:49 AM hi guys, I just read ur comments. If I have been told to describle Speed grade in a sentence,I would say " Its a minimum i/o delay". This means a signal will take atleast this much of time to travel from i/p to o/p. From: gauravkshri Posted : 11/9/2006 1:21:26 AM hi, You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see "3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.) For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay. The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster. http://www.xess.com/faq/M0000236.HTM

 

 

转自于：

http://203.208.35.101/search?q=cache:09KpUgWaDgwJ:www.vlsibank.com/sessionspage.asp%3Ftitl_id%3D10957+xilinx+speed+grade&hl=zh-CN&ct=clnk&cd=5&gl=cn&st_usg=ALhdy29YqtX7xptt5vtPPWCwct6a8sM5Tg

 

转自：http://blog.sina.com.cn/s/blog_5e9a27140100c743.html

===================================================================

 

[合集] FPGA中，速度等级代表了什么？
发信人: zhaoguangjie (赵广杰), 信区: FPGATech
标  题: [合集] FPGA中，速度等级代表了什么？
发信站: 水木社区 (Mon Mar 24 14:29:25 2008), 站内

☆─────────────────────────────────────☆
   pebble001 (pebble001) 于  (Wed Aug 29 14:02:29 2007)  提到:


在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？

比如-6，-7与-8的EP2C8,在使用时具体有什么区别？

谢谢！




☆─────────────────────────────────────☆
   honest41 (当索爱遇见诺基亚) 于  (Wed Aug 29 16:43:30 2007)  提到:

altera的速度等级都是比较抽象的等级，不好说具体表示有多快，不过值越小越快,8是最慢的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！
: ...................



☆─────────────────────────────────────☆
   WeiWei (TISSOT) 于  (Wed Aug 29 16:44:02 2007)  提到:


是不是时延特性？

【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
: altera的速度等级都是比较抽象的等级，不好说具体表示有多快，不过值越小越快,8是最慢的




☆─────────────────────────────────────☆
   pebble001 (pebble001) 于  (Wed Aug 29 17:52:23 2007)  提到:


那在具体选型时怎么考虑呢？

-7与-8之间具体有什么差异呢？

选芯片时就选能得到的最快的？

谢谢！

【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
: altera的速度等级都是比较抽象的等级，不好说具体表示有多快，不过值越小越快,8是最慢的





☆─────────────────────────────────────☆
   Anmywang (anmy) 于  (Wed Aug 29 18:00:28 2007)  提到:

-6的速度是最快的，-8是最慢的。
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！





☆─────────────────────────────────────☆
   leuse (还是太冲动啊) 于  (Wed Aug 29 18:16:42 2007)  提到:

应该是代表片内的最大延时，-8就表示8ns
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！
: ...................



☆─────────────────────────────────────☆
   newbeesile (blackjack他是谁 ) 于  (Wed Aug 29 18:37:41 2007)  提到:

cpld有这个说法 FPGA基本上没有一个特定指标跟这个等级相关了
【 在 leuse (还是太冲动啊) 的大作中提到: 】
: 应该是代表片内的最大延时，-8就表示8ns




☆─────────────────────────────────────☆
   InterRonaldo (罗那尔多在Inter) 于  (Wed Aug 29 19:08:28 2007)  提到:

补充下，xilinx的FPGA是越大越快

【 在 Anmywang (anmy) 的大作中提到: 】
: -6的速度是最快的，-8是最慢的。




☆─────────────────────────────────────☆
   FabioCapello (我的心看上去是红的) 于  (Wed Aug 29 19:08:40 2007)  提到:

Xilinx是那样吧.
Altera代表的是ns.

【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
altera的速度等级都是比较抽象的等级，不好说具体表示有多快，不过值越小越快,8是最慢的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！
: ...................



☆─────────────────────────────────────☆
   honest41 (当索爱遇见诺基亚) 于  (Wed Aug 29 19:39:01 2007)  提到:

选型时主要还是考经验估计吧，不过同种型号各个速度等级的封装，资源都是一样的，所以不影响做板。到时候大不了-8的不够用-6
【 在 pebble001 (pebble001) 的大作中提到: 】
: 那在具体选型时怎么考虑呢？
: -7与-8之间具体有什么差异呢？
: 选芯片时就选能得到的最快的？
: ...................



☆─────────────────────────────────────☆
   flyingcowboy (敢笑“敢笑杨过不痴情”不痴情) 于  (Wed Aug 29 20:17:04 2007)  提到:

速度快的太难买了
【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
: 选型时主要还是考经验估计吧，不过同种型号各个速度等级的封装，资源都是一样的，所以不影响做板。到时候大不了-8的不够用-6





☆─────────────────────────────────────☆
   pebble001 (pebble001) 于  (Wed Aug 29 22:11:02 2007)  提到:


有的封装只有一个速度等级
换速度等级就得换封装，重新画板子啊~


【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
: 选型时主要还是考经验估计吧，不过同种型号各个速度等级的封装，资源都是一样的，所以不影响做板。到时候大不了-8的不够用-6





☆─────────────────────────────────────☆
   pebble001 (pebble001) 于  (Wed Aug 29 22:17:13 2007)  提到:

还是没明白速度等级到底和什么相关，代表了什么:(

比如本该用-7的，我用成了-8的，会有什么坏处？

是片内最高执行频率降低了？还是什么其他的影响？



【 在 honest41 (当索爱遇见诺基亚) 的大作中提到: 】
: 选型时主要还是考经验估计吧，不过同种型号各个速度等级的封装，资源都是一样的，所以不影响做板。到时候大不了-8的不够用-6





☆─────────────────────────────────────☆
   oBigeyes (以不变应万变) 于  (Wed Aug 29 22:18:06 2007)  提到:

片内速度和io速度可能都影响

【 在 pebble001 (pebble001) 的大作中提到: 】
: 还是没明白速度等级到底和什么相关，代表了什么:(
: 比如本该用-7的，我用成了-8的，会有什么坏处？
: 是片内最高执行频率降低了？还是什么其他的影响？
: ...................



☆─────────────────────────────────────☆
   tangtseng (土豆) 于  (Wed Aug 29 22:36:12 2007)  提到:

没有特别的含义。只是在fpga生产后进行了筛选，分处了三个等级，然后标不同的价格。
不同级别只有相对比较的意思，没有延迟的概念。我是这么理解的。他们的FAE也是这么解释的。
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！





☆─────────────────────────────────────☆
   djay (伊泰（900948）) 于  (Sat Sep  8 15:55:22 2007)  提到:

大家都是做FPGA应用的么,还要画板子?
我们用的一般都是别人公司做好的,比如美国的DINI和瑞典的HARDY公司的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 有的封装只有一个速度等级
: 换速度等级就得换封装，重新画板子啊~




☆─────────────────────────────────────☆
   JDAM (billow2) 于  (Mon Sep 17 16:46:20 2007)  提到:

记得好像是0.X纳秒吧...
当时做个项目，用EP1C12-8俊龙的介绍说-8是每过一个LUT0.8ns，好像
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等级具体代表什么意义？是内部最高执行频率的限制吗？
: 比如-6，-7与-8的EP2C8,在使用时具体有什么区别？
: 谢谢！

转自：http://www.newsmth.net/bbsanc.php?path=%2Fgroups%2Fsci.faq%2FFPGATech%2FAltera%2FM.1206340165.i0

 

=======================================================================================

xilinx fpga speed grade

Can anyone please explain what a speed grade is?
If i tell you my bicycle has a speed grade of 29, you'll probably say something like: "Good for you.", but you wouldn't have a clue about what i just said.
So, can you explain to me how i should see the speed grades.
What do they stand for?
Who defines the speed grades?
Can i compare the speed grades between manufacturers?

I can't seem to be able to find anything about the subject anywhere...
There is no consistent definition of a speed grade for all devices. Even for Xilinx, speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Arthur

Jasper,

As Arthur indicated, it is a relative term that is really dependent on the specific family:

-for CPLDs, it is generally pin-to-pin delays in nanoseconds (lower # = faster)

-for old Xilinx FPGAs (pre-Virtex), lower # was faster

-for modern (Virtex and later) FPGAs, the higher # is faster.

The speed grade influences a variety of timing paramters in the FPGA, including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other resources parameters.

You really need to consult the specific datasheet to see specific details for timing based on associated speed grades.

For example, Virtex-4 speed grades are -10 (slowest), -11, and -12 (fatest)

Virtex-5 spede grades are -1 (slowest), -2, and -3 (fastest)

There is no correlation between these numbers. It is really a relative metric of performance within a specific family.

Cheers,

bt

 

转自：http://hi.baidu.com/kinglongzh/blog/item/4fd960865d8bb33867096ed1.html

===================================================================

 

最初接触speed grade这个概念时，很是为Altera的-6、-7、-8速度等级逆向排序的方法困惑过一段时间。不很严密地说，“序号越低，速度等级越高”这是Altera FPGA的排序方法，“序号越高，速度等级也越高”这是Xilinx FPGA的排序方法。 riple

从那时起，就一直没搞明白speed grade是怎么来的，唯一的概念是：同一款芯片可以有多个速度等级，不同的速度等级代表着不同的性能，不同的性能又导致芯片价格的巨大差异。脑子里总有一个模模糊糊的推测：FPGA厂家为了提高利润，专门给同一款芯片生产了不同的速度等级。 riple

直到一年前和一位学过IC设计的同事hammer讨论这一问题时，才有了新的认识：对FPGA厂家来说，为了得到同一款芯片的不同速度等级而专门设计不同的芯片版图是不划算的；所以芯片的速度等级不应该是专门设计出来的，而应该是在芯片生产出来之后，实际测试标定出来的；速度快的芯片在总产量中的比率低，价格也就相应地高。 riple

这一解答很是合理，纠正了我

的一个错误认识。但是我仍然有两点困惑：1. 是什么因素导致了同一批芯片的性能差异；2. 如果因素已知，为什么不人为控制这些因素，提高高速芯片的产率，达到既增加芯片厂商的利润又降低高速芯片价格的目的呢。 riple

前些天在博客里看到huge朋友的一篇FPGA speed grade，激发了我进一步探索上述问题的动力。通过在网络上搜索，逐步得到了以下一些认识： riple

1. 芯片的速度等级决定于芯片内部的门延时和线延时，这两个因素又决定于晶体管的长度L和容值C，这两个数值的差异最终决定于芯片的生产工艺。怎样的工艺导致了这一差异，我还没找到答案。 riple

2. 在芯片生产过程中，有一个阶段叫做speed binning。就是采用一定的方法、按照一组标准对生产出来的芯片进行筛选和分类，进而划分不同的速度等级。“测试和封装”应该就包含这一过程。 riple

    关于speed binning的技术有很多专利： riple

    Integrated circuit with adaptive speed binning

    Semiconductor device with speed binning test circuit and test method thereof

    Binning for semi-custom ASICs

    Method and apparatus for determining wafer quality profiles

    Method of sorting dice by speed during die bond assembly and packaging to customer order

    Method for prioritizing production lots based on grade estimates and output requirements

3. 速度等级的标定不仅仅取决于芯片本身的品质，还与芯片的市场定位有很大关系，返修概率和成本也是因素之一。 riple

4. 芯片的等级可以在测试后加以具体调整和改善，在存储器芯片的生产中这一技术应用很广泛。 riple

5. 芯片生产的过程是充满各种变数的，生产过程可以得到控制，但是控制不可能精确到一个分子、一个原子，产品质量只能是一个统计目标。同一个wafer上的芯片会有差异，即使是同一芯片的不同部分也是有差异的。速度等级是一个统计数字，反映了一批芯片的某些共同特性，不代表个别芯片的质量。而且由于某些芯片的测试是抽样进行的，也不排除个别芯片的个别性能会低于标定的速度等级。不过，据说FPGA的测试是极严格的，很可能我们拿到手的芯片个个都经过了详尽的测试。这也是FPGA芯片价格高于普通芯片的原因。 riple

6. 同一等级的芯片中的绝大多数，其性能应该高于该速度等级的划分标准。这也是为什么在FPGA设计中，有少许时序分析违规的设计下载到芯片中仍然能够正常运行的原因（时序分析采用的模型参数是芯片的统计参数，是最保守也是最安全的）。不过，由于同一等级的芯片仍然存在性能差异，存在时序违规但是单次测试成功的FPGA设计不能确保在量产时不在个别芯片上出现问题（出了问题就要返修或现场调查，成本一下子就上去了）。所以，还是要把时序收敛了才能放心量产，这就是工程标准对产品质量的保证。 riple

7. 概率和统计学源于工程实践，对工程实践又起到了巨大的指导作用。工程实践中的标准都是前人经验教训的积累，是人类社会的宝贵精神财富。 riple

8. 现实世界是模拟的，不是数字的。在考察现实问题时，我们这些数字工程师和软件工程师应该抛弃“一是一、〇是〇”的观念，用连续的眼光看待这个连续变化的真实世界。 riple

9. 芯片生产过程中的不确定性导致了芯片的性能差异，这一差异影响了芯片的价格，价格和性能的折中又影响了我们这些FPGA设计工程师在器件选型、设计方法上的决策，我们生产的产品的性价比决定了产品的销售，产品的销量又决定了芯片的采购量，采购量又影响了芯片的采购价格...。原子、分子级别上的差异，就这样一级一级地传递和放大。人类社会就是这样环环相扣，互相制约的。嘿，真是神奇！

 

转自：http://wenku.baidu.com/view/ea793deef8c75fbfc77db263.html