//头文件省略,感觉DM9000的代码写的比较简单
//放在u-boot里看比较合适,和上层的接口较少,且没有虚实地址转换,较容易理解
enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
8, DM9000_1M_HPNA = 0x10
};
enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
};
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
u32 runt_length_counter; /* counter: RX length < 64byte */
u32 long_length_counter; /* counter: RX length > 1514byte */
u32 reset_counter; /* counter: RESET */
u32 reset_tx_timeout; /* RESET caused by TX Timeout */
u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
u16 tx_pkt_cnt;
u16 queue_start_addr;
u16 dbug_cnt;
u8 phy_addr;
u8 device_wait_reset; /* device state */
u8 nic_type; /* NIC type */
unsigned char srom[128];
} board_info_t;
board_info_t dmfe_info;
/* For module input parameter */
static int media_mode = DM9000_AUTO;
static u8 nfloor = 0;
/* function declaration 有这么几个函数要看------------------------------------- */
int eth_init(bd_t * bd);
int eth_send(volatile void *, int);
int eth_rx(void);
void eth_halt(void);
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
u16 read_srom_word(int);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);
/* DM9000 network board routine ---------------------------- */
#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
#define DM9000_inb(r) (*(volatile u8 *)r)
#define DM9000_inw(r) (*(volatile u16 *)r)
#define DM9000_inl(r) (*(volatile u32 *)r)
/*
先看最基本的读写函数
Read a byte from I/O port
读一个byte数据
*/
static u8
DM9000_ior(int reg)
{
DM9000_outb(reg, DM9000_IO); //首先发送地址
return DM9000_inb(DM9000_DATA); //然后读取数据,看时序图,感觉时序要求蛮高
}
/*
Write a byte to I/O port
向I/O口写一个btye数据
*/
static void
DM9000_iow(int reg, u8 value)
{
DM9000_outb(reg, DM9000_IO); //发送要写入的地址
DM9000_outb(value, DM9000_DATA); //再发送数据
}
/*
Read a word from phyxcer
从phy芯片中读取16bit数据
*/
static u16
phy_read(int reg)
{
u16 val;
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); //EEPROM & PHY Address Register 确定读取地址
//#define DM9000_PHY 0x40 /* PHY address 0x01 */
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ //EEPROM & PHY Control Register 0b1100 选中并读取phy eeprom
udelay(100); /* Wait read complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ //根据数据手册上描述,操作完成后需要清零
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); //EEPROM & PHY High Byte Data Register 读取高位和低位寄存器
/* The read data keeps on REG_0D & REG_0E */
DM9000_DBG("phy_read(%d): %d/n", reg, val);
return val;
}
/*
Write a word to phyxcer
向phy芯片中写入16bit数据
*/
static void
phy_write(int reg, u16 value)
{
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); //同上,确定地址
/* Fill the written data into REG_0D & REG_0E */
DM9000_iow(DM9000_EPDRL, (value & 0xff)); //先将数据放进入
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ //0b1010 先选中并进行写操作
udelay(500); /* Wait write complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ //写时间长一点,延时500us,再清零
DM9000_DBG("phy_write(reg:%d, value:%d)/n", reg, value);
}
/*
Search DM9000 board, allocate space and register it
probe函数
*/
int
dm9000_probe(void)
{
u32 id_val; //32bit变量
id_val = DM9000_ior(DM9000_VIDL); //首先读VIDL vendor ID low byte
id_val |= DM9000_ior(DM9000_VIDH) << 8; //然后读VIDH vendor ID high byte
id_val |= DM9000_ior(DM9000_PIDL) << 16; //再读PIDL Product ID low byte
id_val |= DM9000_ior(DM9000_PIDH) << 24; //最后读PIDH Product ID high byte
if (id_val == DM9000_ID) { //#define DM9000_ID 0x90000A46 和这个比较看看读出的对不对
printf("dm9000 i/o: 0x%x, id: 0x%x /n", CONFIG_DM9000_BASE, //BASE地址应该是 0x18000000
id_val);
return 0;
} else {
printf("dm9000 not found at 0x%08x id: 0x%08x/n",
CONFIG_DM9000_BASE, id_val);
return -1;
}
}
/* Set PHY operationg mode
设置PHY的工作模式
*/
static void
set_PHY_mode(void)
{
u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
if (!(media_mode & DM9000_AUTO)) { //竟然用全局变量而不是传参,会被老板打批的
switch (media_mode) {
case DM9000_10MHD:
phy_reg4 = 0x21; //设置双工、半双工
phy_reg0 = 0x0000; //phy寄存器0是设置速度模式
break;
case DM9000_10MFD:
phy_reg4 = 0x41;
phy_reg0 = 0x1100;
break;
case DM9000_100MHD:
phy_reg4 = 0x81;
phy_reg0 = 0x2000;
break;
case DM9000_100MFD:
phy_reg4 = 0x101;
phy_reg0 = 0x3100;
break;
}
phy_write(4, phy_reg4); /* Set PHY media mode */ //写phy 04寄存器
phy_write(0, phy_reg0); /* Tmp */ //写phy 00寄存器
}
DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ //General Purpose Control Register (in 8-bit mode)
//奇怪,第0位应该是reserved,GPIO都应该是输入?
//找到说明:GPIO0默认为输出做POWER_DOWN功能
DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ //写0使能phy芯片
}
/*
Init HomeRun DM9801
*/
static void program_dm9801(u16 HPNA_rev)
{
//应该用不到9801,省略
}
/*
Init LongRun DM9802
*/
static void program_dm9802(void)
{
//应该用不到9802,省略
}
/* Identify NIC type 确定NIC类型
*/
static void identify_nic(void)
{
struct board_info *db = &dmfe_info; /* Point a board information structure */
u16 phy_reg3;
DM9000_iow(DM9000_NCR, NCR_EXT_PHY); //Network Control Register
//#define NCR_EXT_PHY (1<<7)
//奇怪,DM9000a的这一位又是reserved
phy_reg3 = phy_read(3);
switch (phy_reg3 & 0xfff0) { //读phyid,判断是不是9801或者9802,应该都不是,初始化时没看到
case 0xb900:
if (phy_read(31) == 0x4404) {
db->nic_type = HOMERUN_NIC;
program_dm9801(phy_reg3);
DM9000_DBG("found homerun NIC/n");
} else {
db->nic_type = LONGRUN_NIC;
DM9000_DBG("found longrun NIC/n");
program_dm9802();
}
break;
default:
db->nic_type = FASTETHER_NIC; //type = 0
break;
}
DM9000_iow(DM9000_NCR, 0);
}
/* General Purpose dm9000 reset routine */
static void dm9000_reset(void)
{
DM9000_DBG("resetting/n");
DM9000_iow(DM9000_NCR, NCR_RST); //复位
udelay(1000); /* delay 1ms */
}
/* Initilize dm9000 board
*/
int eth_init(bd_t * bd)
{
int i, oft, lnk;
DM9000_DBG("eth_init()/n");
/* RESET device */
dm9000_reset(); //复位
dm9000_probe(); //检测网络连接类型
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic(); //检测NIC类型
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode(); //设置工作模式
/* Program operating register */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ //清零
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ //清零
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ //Back Pressure Threshold Register背压门限寄存器
//当接收SRAM空闲空间低于该门限值,则MAC将产生一个拥挤状态。
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
//溢出控制门限寄存器(Flow Control Threshold Register)
//7-4:HWOT:接收FIFO缓存溢出门限最高值。
//当接收SRAM空闲空间小于该门限值,则发送一个暂停时间(pause_time)为FFFFH的暂停包。
//若该值为0,则无接收空闲空间。1=1K字节。默认值为3H,即3K字节空闲空间。不要超过SRAM大小。
//3-0:LWOT:接收FIFO缓存溢出门限最低值。
//当接收SRAM空闲空间大于该门限值,则发送一个暂停时间(pause_time)为0000H的暂停包。
//当溢出门限最高值的暂停包发送之后,溢出门限最低值的暂停包才有效。默认值为8K字节。不要超过SRAM大小。
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
//接收溢出控制寄存器(RX Flow Control Register)
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
//特殊模式控制寄存器(Special Mode Control Register)
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
//网络状态寄存器(Network Status Register )清零TX
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
//清空中断标志位,u-boot里也没有用中断
/* 从u-boot中读取MAC地址 */
char *s, *e;
s = getenv ("ethaddr");
for (i = 0; i < 6; ++i) {
bd->bi_enetaddr[i] = s ?
simple_strtoul (s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
/*输出MAC地址*/
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x/n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("/n");
/* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
//RCR(05H):接收控制寄存器(RX Control Register )
//丢弃长数据包,丢弃CRC校验错误数据包,接受使能
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask 中断屏蔽寄存器(Interrupt Mask Register)*/
//值使能了一个PAR中断,其他比如接受中断都没有使能
i = 0;
//获取网络类型
/* while (!(phy_read(1) & 0x20)) {
udelay(1000);
i++;
if (i == 10000) {
printf("could not establish link/n");
return 0;
}
}
*/
/* see what we've got */
lnk = phy_read(17) >> 12;
/* printf("operating at ");
switch (lnk) {
case 1:
printf("10M half duplex ");
break;
case 2:
printf("10M full duplex ");
break;
case 4:
printf("100M half duplex ");
break;
case 8:
printf("100M full duplex ");
break;
default:
printf("unknown: %d ", lnk);
break;
}
printf("mode/n");
*/
return 0;
}
/*
Hardware start transmission.
Send a packet to media from the upper layer.
发送函数
*/
int eth_send(volatile void *packet, int length)
{
char *data_ptr;
u32 tmplen, i;
int tmo;
DM9000_DBG("eth_send: length: %d/n", length); //数据包长度
for (i = 0; i < length; i++) {
if (i % 8 == 0)
DM9000_DBG("/nSend: 02x: ", i);
DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
} DM9000_DBG("/n");
/* Move data to DM9000 TX RAM */
data_ptr = (char *) packet; //传递指针
DM9000_outb(DM9000_MWCMD, DM9000_IO); //存储器读地址自动增加的读数据命令,选中地址
//(Memory Data Write Command With Address Increment Register)
//7-0:MWCMD:写数据到发送SRAM中,之后指向内部SRAM的读指针自动增加1、2或4,
//根据处理器的操作模式而定(8位、16位或32位)。
tmplen = (length + 1) / 2; //16bit mode 重新计算长度
for (i = 0; i < tmplen; i++)
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); //开始发送数据
/* Set TX length to DM9000 */
DM9000_iow(DM9000_TXPLL, length & 0xff); //把发送长度写入TX寄存器
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
/* Issue TX polling command */
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete 发送控制寄存器(TX Control Register)*/
//TXREQ:TX(发送)请求。发送完成后自动清零该位。
/* wait for end of transmission */
tmo = get_timer(0) + 5 * CFG_HZ;
while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { //判断是否发送完成
if (get_timer(0) >= tmo) { //判断是否超时
printf("transmission timeout/n");
break;
}
}
DM9000_DBG("transmit done/n/n");
return 0;
}
/*
Stop the interface.
The interface is stopped when it is brought.
停止网络功能,被我kill掉了,否则每次传输完成都要halt
*/
void eth_halt(void)
{
DM9000_DBG("eth_halt dummy by kyon/n");
/* RESET devie */
//phy_write(0, 0x8000); /* PHY RESET */
//DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
//DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
//DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
}
/*
Received a packet and pass to upper layer
最重要的接收函数
*/
int eth_rx(void)
{
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
u16 RxStatus, RxLen = 0;
u32 tmplen, i;
DM9000_ior(DM9000_MRRH); //kyon //存储器读地址寄存器高半字节,dummy read?这儿是我自己后加上
DM9000_ior(DM9000_MRRL);
do{ //do循环也是我自己后加的
/* Check packet ready or not */
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
//存储器地址不变的读数据命令,这次是真的dummy read一下,怀疑这句要放在do 外面
rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
//不太理解这儿读到的是什么东西,应该是数据,如果读到0就返回,在网上搜了下:
// DM9000A接收缓冲区中的数据格中格式是4字节的包头+真正的数据.
// 其中4字节包头分别位为: rxbyte, status, count_low, count_hight
// 说明如下:
// rxbyte: 0-没有接收到数据, 1-有新的数据包
// status: 状态
// count_low, count_hight: 接收到的数据长度
if (rxbyte == 0)
return 0;
/* Status check: this byte must be 0 or 1 */
if (rxbyte > 1) { //如果rxbyte大于1,关闭设备,也就是说正常的话rxbyte应该为1
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
DM9000_DBG("rx status check: %d/n", rxbyte);
}
DM9000_DBG("receiving packet/n");
/* A packet ready now & Get status/length 如果一个数据包已经准备好,也就是说前面判断数据包是否准备好*/
DM9000_outb(DM9000_MRCMD, DM9000_IO);
//存储器读地址自动增加的读数据命令 准备IO地址
/* */
RxStatus = DM9000_inw(DM9000_DATA); //获取RX状态
RxLen = DM9000_inw(DM9000_DATA); //获取RX数据包长度
/* */
DM9000_DBG("rx status: 0x%04x rx len: %d/n", RxStatus, RxLen);
/* Move data from DM9000 */
/* Read received packet from RX SRAM */
tmplen = (RxLen + 1) / 2; //重新计算16bit长度
for (i = 0; i < tmplen; i++) //获取数据
{
((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
//printf("%d ",((u16 *) rdptr)[i]);
}
/* */ //排错处理
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|| (RxLen > DM9000_PKT_MAX)) {
if (RxStatus & 0x100) {
printf("rx fifo error/n");
}
if (RxStatus & 0x200) {
printf("rx crc error/n");
}
if (RxStatus & 0x8000) {
printf("rx length error/n");
}
if (RxLen > DM9000_PKT_MAX) {
printf("rx length too big/n");
dm9000_reset();
}
} else {
/* Pass to upper layer */
DM9000_DBG("passing packet to upper layer/n");
NetReceive(NetRxPackets[0], RxLen); //将数据包传递到上层,
//return RxLen;
}
}
while (rxbyte == DM9000_PKT_RDY); //如果rxbyte == 1 就继续循环
//return 0;
return RxLen;
}
/*
以下两个函数没看到在哪使用的???
Read a word data from SROM
*/
u16 read_srom_word(int offset)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPCR, 0x4);
udelay(8000);
DM9000_iow(DM9000_EPCR, 0x0);
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}
void write_srom_word(int offset, u16 val)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
DM9000_iow(DM9000_EPDRL, (val & 0xff));
DM9000_iow(DM9000_EPCR, 0x12);
udelay(8000);
DM9000_iow(DM9000_EPCR, 0);
}