s3c6410的存储器映射

    Main memory is accessed via SPINE bus, and its address range is from 0x0000_0000 to 0x6FFF_FFFF. This
main memory part is seperated into four areas：

   boot image area, internal memory area, static memory area, anddynamic memory area.

    Address range of boot image area is from 0x0000_0000 to 0x07FF_FFFF, but there is no real mapped-memory.
Boot image area has mirrored image which points a partial region of internal memory area or static memory area.
Start address of boot image is fixed to 0x0000_0000.
     Internal memory area is used to access internal ROM and internal SRAM for boot loader, which is also called
Steppingstone. Start address for each internal memory is fixed. Address range of internal ROM is from
0x0800_0000 to 0x0BFF_FFFF, but real storage is only 32KB. This region is read-only, and can be mapped to
boot image area when internal ROM booting is selected. Address range of internal SRAM is from 0x0C00_0000 to
0x0FFF_FFFF, but real storage is only 4KB.
    Address range of static memory area is from 0x1000_0000 to 0x3FFF_FFFF. SROM, SRAM, NOR Flash,
asyncronous NOR interface device, OneNAND Flash, and Steppingstone can be accessed by this address area.
Each area stands for a chip select, for example, address range from 0x1000_0000 to 0x17FF_FFFF stands for
Xm0CSn[0]. Start address for each chip select is fixed. NAND Flash and CF/ATA cannot be accessed via static
memory area, so if any of Xm0CSn[5:2] is mapped to NFCON or CFCON, related address region should not be
accessed. One exception is that if Xm0CSn[2] is used for NAND Flash, Steppingstone is mirrored to address
region from 0x2000_0000 to 27FF_FFFF.
    Address range of dynamic memory area is from 0x4000_0000 to 0x6FFF_FFFF. DMC1 has right to use address
range from 0x5000_0000 to 0x6FFF_FFFF. Start address for each chip select is configurable.
    Pheripheral is accessed via PERI bus, and its address range is from 0x7000_0000 to 0x7FFF_FFFF.All SFRs
can be accessed in this address range. Also, if data is needed to transfer from NFCON or CFCON, those data
should be transferred via PERI bus.

    通过SPINE 总线访问主存，主存的地址范围是0x0000_0000～0x6FFF_FFFF。主存部分分成四个区域：

引导镜像区、内部存储区、静态存储区和动态存储区。
    引导镜像区的地址范围是从0x0000_0000～0x07FF_FFFF，但是没有实际的映射内存。引导镜像区反映
一个镜像，这个镜像指向内存的一部分区域或者静态存储区。引导镜像的开始地址是0x0000_0000。
    内部存储区用于启动代码访问内部ROM 和内部 SRAM，也被称做Steppingstone。每块内部存储器的
起始地址是确定的。内部ROM 的地址范围是0x0800_0000～0x0BFF_FFFF，但是实际存储仅32KB。该区域

是只读的，并且当内部ROM 启动被选择时，该区域能映射到引导镜像区。内部SRAM 的地址范围是

0x0C00_0000～0x0FFF_FFFF，但是实际存储仅4KB。该区域能被读和写，当NAND 闪存启动被选择时能映射

到引导镜像区。
     静态存储区的地址范围是0x1000_0000～0x3FFF_FFFF。通过该地址区域能访问SROM、SRAM、 NOR Flash、
同步NOR接口设备、和Steppingstone。每一块区域代表一个芯片选择，例如，地址范围从0x1000_0000～
0x17FF_FFFF代表Xm0CSn[0]。每一个芯片选择的开始地址是固定的。NAND Flash和CF/ATAPI不能通过静态
存储区访问，因此任何Xm0CSn[5:2]映射到NFCON 或 CFCON，相关地址区域不应当被访问。一个例外，如果
Xm0CSn[2]用于NAND Flash，Steppingstone映射到存取区从0x2000_0000～27FF_FFFF。
       动态存储区的地址范围是0x4000_0000～0x6FFF_FFFF。DMC0有权使用地址0x4000_0000～
0x4FFF_FFFF，并且DMC1有权使用地址0x5000_0000～0x6FFF_FFFF。对于每一块芯片选择的起始地址是可
以进行配置的。
        外设区域通过PERI 总线被访问，它的地址范围是0x7000_0000～0x7FFF_FFFF。这个地址范围的所有

的SFR 能被访问。而且如果数据需要从NFCON 或CFCON 传输，这些数据需要通过PERI 总线传输。