module TOP200MHz( input clk_in, input rst, output reg ledout ); wire clk50m,clk200m; dcm62in50out dcm62in50out_inst( .CLKIN_IN(clk_in), .CLKFX_OUT(clk50m), .CLKIN_IBUFG_OUT(), .CLK0_OUT(), .LOCKED_OUT() ); dcm50in200out dcm50in200out_inst( .CLKIN_IN(clk50m), CLKFX_OUT(clk200m), CLKIN_IBUFG_OUT(), CLK0_OUT(), LOCKED_OUT() ); always @ (posedge clk200m) if(!rst) begin ledout <= 0;end else begin ledout <= ~ledout; end endmodule
代码如上,写了测试代码,在modelsim中仿真,测试代码如下:
module test_top200mhz_1st; // Inputs reg clk_in; reg rst; // Outputs wire ledout; // Instantiate the Unit Under Test (UUT) TOP200MHz uut ( .clk_in(clk_in), .rst(rst), .ledout(ledout) ); initial begin // Initialize Inputs clk_in = 0; rst = 1; // Wait 100 ns for global reset to finish #100; rst = 0; #20; rst = 1; // Add stimulus here end always #4 clk_in = ~clk_in; endmodule
ModelSim中出错如下:
# ** Error: TOP200MHz.v(37): near "CLKFX_OUT": syntax error, unexpected "IDENTIFIER", expecting ".*" or '.'
# ** Error: C:/Modeltech_6.2b/win32/vlog failed.
其实错误很简单,如果在ISE中对代码进行语法检查,则可得如下错误报告:
ERROR:HDLCompilers:26 - "TOP200MHz.v" line 39 expecting '.', found 'CLKFX_OUT'
检查一下代码,原来是dcm50in200out模块在例化时后面几个端口前面没加“.”,小错误呀,网上还搜不到解决方案呢。。。
所以仿真前最起码应该先检查语法通过后再仿真嘛,或者综合通过后更保险啦……