SPI Block Guide V04.01 - 01

©Motorola, Inc., 2001

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Section 1 Introduction

Figure1-1 gives an overview on the SPI architecture. Themain parts of the SPI are status, control and data registers, shifter logic,baud rate generator, master/slave control logic and port control logic.

Figure1-1 SPI Block Diagram

 

1.1 Overview

 

The SPI module allows a duplex,synchronous, serial communication between the MCU and peripheral devices.Software can poll the SPI status flags or the SPI operation can be interruptdriven.

 

 

 

 

1.2 Features

 

The SPI includes these distinctivefeatures:

l          Master mode and slave mode

l          Bi-directional mode

l          Slave select output

l          Mode fault error flag with CPUinterrupt capability

l          Double-buffered data register

l          Serial clock with programmablepolarity and phase

l          Control of SPI operation duringwait mode

 

1.3 Modes of Operation

 

The SPI functions in three modes, run,wait, and stop.

l          Run Mode

This is thebasic mode of operation.

l          Wait Mode

SPI operation inwait mode is a configurable low power mode, controlled by the SPISWAI bitlocated in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, theSPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into apower conservative state, with the SPI clock generation turned off. If the SPIis configured as a master, any transmission in progress stops, but is resumedafter CPU goes into Run Mode. If the SPI is configured as a slave, receptionand transmission of a byte continues, so that the slave stays synchronized tothe master.

l          Stop Mode

 

The SPI is inactive in stop mode forreduced power consumption. If the SPI is configured as a master, anytransmission in progress stops, but is resumed after CPU goes into Run Mode. Ifthe SPI is configured as a slave, reception and transmission of a bytecontinues, so that the slave stays synchronized to the master.

 

This is a high level description only,detailed descriptions of operating modes are contained in section 4.8 LowPower Mode Options.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Section 2 External SignalDescription

 

2.1 Overview

 

This section lists the name and descriptionof all ports including inputs and outputs that do, or may, connect off chip.The SPI module has a total of 4 external pins.

 

 

2.2 Detailed Signal Description

 

2.2.1 MOSI

 

This pin is used to transmit data out ofthe SPI module when it is configured as a Master and receive data when it isconfigured as Slave.

 

2.2.2 MISO

 

This pin is used to transmit data out ofthe SPI module when it is configured as a Slave and receive data when it isconfigured as Master.

 

2.2.3

 

This pin is used to output the selectsignal from the SPI module to another peripheral with which a data transfer isto take place when its configured as a Master and its used as an input toreceive the slave select signal when the SPI is configured as Slave.

 

2.2.4 SCK

 

This pin is used to output the clock withrespect to which the SPI transfers data or receive clock in case of Slave.