ARM instruction set

The ARM instruction set can be divided into six broad classes of instruction:

Arm指令集分成了六大类
• Branch instructions

   除了跳转还包括了指令集之间的切换，Thumb <-> ARM
• Data-processing instructions on page A1-7

    • Arithmetic/logic instructions
    • Comparison instructions
    • Single Instruction Multiple Data (SIMD) instructions
    • Multiply instructions on page A1-8
    • Miscellaneous Data Processing instructions on page A1-8.
• Status register transfer instructions on page A1-8

在通用寄存器和状态寄存器之间倒换数据

    • set the values of the condition code flags
    • set the values of the interrupt enable bits
    • set the processor mode and state
    • alter the endianness of Load and Store operations.
• Load and store instructions on page A1-8

    • Load and Store Register 寄存器和内存之间的值的读写
    • Load and Store Multiple registers on page A1-9  一次读存多个
    • Load and Store Register Exclusive on page A1-9， 提供了原子操作.
• Coprocessor instructions on page A1-10

     Data-processing instructions
                   These start a coprocessor-specific internal operation.
     Data transfer instructions
                   These transfer coprocessor data to or from memory. The address of the transfer is calculated
                    by the ARM processor.
     Register transfer instructions
                   These allow a coprocessor value to be transferred to or from an ARM register, or a pair of
                   ARM registers.
• Exception-generating instructions on page A1-10.

    Software interrupt instructions
        SWI instructions cause a software interrupt exception to occur. These are normally used to
        make calls to an operating system, to request an OS-defined service. The exception entry
        caused by a SWI instruction also changes to a privileged processor mode. This allows an
        unprivileged task to gain access to privileged functions, but only in ways permitted by the
        OS.
    Software breakpoint instructions
        BKPT instructions cause an abort exception to occur. If suitable debugger software is installed
        on the abort vector, an abort exception generated in this fashion is treated as a breakpoint.
        If debug hardware is present in the system, it can instead treat a BKPT instruction directly as
        a breakpoint, preventing the abort exception from occurring.

        Most data-processing instructions and one type of coprocessor instruction can update the four condition
        code flags in the CPSR (Negative, Zero, Carry and oVerflow) according to their result.

 

且arm指令大多有条件执行的判断。
Almost all ARM instructions contain a 4-bit condition field. One value of this field specifies that the
instruction is executed unconditionally.
Fourteen other values specify conditional execution of the instruction. If the condition code flags indicate
that the corresponding condition is true when the instruction starts executing, it executes normally.
Otherwise, the instruction does nothing. The 14 available conditions allow:
• tests for equality and non-equality
• tests for <, <=, >, and >= inequalities, in both signed and unsigned arithmetic
• each condition code flag to be tested individually.

啥是alternative instructions?
The sixteenth value of the condition field encodes alternative instructions. These do not allow conditional
execution. Before ARMv5 these instructions were UNPREDICTABLE.