Broadcom SDK编译
Broadcom提供了工具链和源码以及编译工具
需要先编译工具链再编译源码，过程会比较繁琐而且耗时
一.编译环境
关于编译环境，在刘英凯的ubuntu10.04和我的ubuntu12.04均编译通过
刘英凯编译的toolchains在我的电脑上编译代码时会有很多问题，所以toolchains是我重新编译的
工具链的可移动性有待验证 二.toolchains编译 $mkdirtoolchain_src/glibcCopytheiProc_glibc_toolchain
.tar.gz file into the newly created toolchain directory and untar the file:
$ cp XLDK/buildroot/dl/iProc_glibc_toolchain.tar.gz toolchain_src/ glibc/
$ cd toolchain_src/glibc
$ tar –xvzf iProc_glibc_toolchain.tar.gz
Ch
an
ge to the buildroot directory under toolchain_src/glibc:
$ cd buildroot
Lo
ad the toolchain build configuration:
$ make iproc-tools_defconfig
Ch
an
ge the Host Directory (BR2_HOST_DIR) to the new install directory via menuconfig:
$ make menuconfig //Build option 不需要更改， 默认为当前目录下的host文件夹
Ch
an
ge ‘Build options’->’Host dir’ to a directory in which to install the glibc toolchain
(<glibc_47x_toolchain_install_dir>).
Save and exit.
Bu
ild
the toolchain:
$ make
耗时
3.5h，中间需要联网下载一些源码，切勿断网，切勿中断，未编译完成的工具链也会出现各种问题
三.内核编译
Lo
ad the buildroot configuration file:
$ make $CHIP-<target type>_defconfig //make saber2-nfs_defconfig
Mo
dify the configuration to indicate glibc libraries are being used.
$ make menuconfig
Ch
an
ge ‘Toolchain’->’External toolchain C library’ to glibc/eglibc
Save and exit.
$make
耗时
3h左右，中间需要联网下载一些源码和工具，切勿断网，切勿中断
1.报错 struct siginfo not complete
将/h
ome/kevin/works/projects/XLDK-3.6.2/XLDK/buildroot/output/toolchain/gdb-7.4.1/gdb/linux-nat.c
linux-nat.h
/home/kevin/works/projects/XLDK-3.6.2/XLDK/buildroot/output/toolchain/gdb-7.4.1/gdb/gdbserver/linux-low.c
中的所有struct siginfo 改为 siginfo_t
2.缺少mkimage
在工具链
make menuconfig 设置编译
但我编译后
host/usr/bin下面未生成mkimage
最后在
ubutnu上安装了uboot-tools
用的系统默认的
$ mkimage -A arm-O linux -T kernel -n Image -a 0x61008000 -C none -d output/images/Image output/images/uImage_nfs.img
3.nfs
环境变量nfs=sete
nv bootargs console=ttyS0,115200n8 maxcpus=1 mem=480M
ip=192.168.0.22:192.168.0.99:192.168.0.1:255.255.255.0:northstar:eth0 root=/dev/nfs rw
nfsroot=192.168.0.99:/home/kevin/nfs;tftpboot uImage_nfs.img;bootm
PC上需要安装nfs server将image下的rootfs.tar解压到nfs目录下
四.u-boot for ram
1.修改uboot代码段地址
将XL
DK-3.6.2/XLDK/bootloader/u-boot-2012.10-rc3/board/broadcom/bcm95626x/config.mk
CONFIG_SYS_TEXT_BASE = 0xF0000000
改为CON
FI
G_
SYS_TEXT_BASE = 0x70000000
（由于tftp默认的load addr=0x70000000，所以目前将u-boot代码段的地址也改为这个地址）
2.栈地址修改
include/configs/saber2.h中150左右
//#
define CONFIG_SYS_INIT_SP_ADDR (CONFIG_PHYS_SDRAM_0 + CONFIG_SYS_STACK_SIZE - 16)
#define CONFIG_SYS_INIT_SP_ADDR (0x78000000 + CONFIG_SYS_STACK_SIZE - 16)
3.修改初始化问题
将XL
DK-3.6.2/XLDK/bootloader/u-boot-2012.10-rc3/board/broadcom/bcm95626x/m95626x.c
int dram_init (void)函数中的
//
ddr_init2(); //注释掉
以下为正常启动打印:
U-Boot 2012.10 (May 18 2015 - 11:47:14)
DEV ID = 0xb460
SKU ID = 0xb460
DDR type: DDR3
MEMC 0 DDR speed = 667MHz
PHY revision version: 0x00a1f001
ddr_init2: Calling soc_and28_shmoo_dram_info_set
ddr_init2: Calling soc_and28_shmoo_phy_init
A Series - PHY Initialization (PHY index: 00)
A01. Turn off CKE
A02. Configure timing parameters
A03. Configure PHY PLL
PHY PLL Configuration
Fref.............: 50 MHz
Data rate........: 1333 Mbps
PLL locked.
A04. Configure reference voltage
A05. Compute VDL step size
VDL calibration complete.
VDL step size....: 11.541 ps
UI size..........: 65.000 steps
A06. Configure ADDR/CTRL VDLs
A07. Disable Virtual VTT
A08. ZQ calibration
P drive..........: 0x10
N drive..........: 0x10
P termination....: 0x06
N termination....: 0x06
P idle...........: 0x00
N idle...........: 0x00
A09. Configure Static Pad Control
A10. Configure ODT
A11. Configure Write Pre-/Post-amble
A12. Configure Auto Idle
A13. Release PHY control
A Series - PHY Initialization complete (PHY index: 00)
Programming controller register
ddr_init2: MemC initialization complete
ddr_init2: Calling soc_and28_shmoo_ctl
Va
lidate Shmoo parameters stored in flash ..... OK
Press Ctrl-C to run Shmoo ..... skipped
DDR Tuning Complete
Running simple memory test ..... OK
DDR Interface Ready
DRAM: 2 GiB
WA
RNING: Caches not enabled
Flash: PNOR flash is not present - switch decoding bit back for NAND
NAND: Micron MT29F16G08CBACA, blocks per lun: 800 lun count: 1
*ERROR* Invalid strap options for this NAND: page=0 type=13
Ove
rriding invalid strap options: strap_type=6
1024 KiB blocks, 4 KiB pages, 27B OOB, 8-bit
NAND: chipsize 2048 MiB
SF: Detected N25Q256 with page size 64 KiB, total 32 MiB
In: serial
Out: serial
Err: serial
arm_clk=1000MHz, axi_clk=400MHz, apb_clk=100MHz, arm_periph_clk=500MHz
DDR Tuning Complete
TOP_XGXS0_PLL_CONTROL_3 = 0x4a5000
TOP_UC_TAP_CONTROL = 0x3a
TOP_SWITCH_FEATURE_ENABLE_3 = 0x5d99c00
Net: Registering eth
Broadcom BCM IPROC Ethernet driver 0.1
et0: Initial GMAC 0, base address:0x18042000
et0: ethHw_chipAttach: Chip ID: 0xb460; phyaddr: 0x1
et0: gmac_serdes_init() serdes_status0: 0x0; serdes_status1: 0x100
bcmiproc_eth-0
========== relocate address: 0xdff90000, offset 0xc1f90000 ==========
Hit any key to stop autoboot: 0
##
Booting kernel from Legacy Image at f0100000 ...
Image Name: XLDK_src_3.6.2
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 6205252 Bytes = 5.9 MiB
Load Address: 61008000
Entry Point: 61008000
Ve
rifying Checksum ... OK
Loading Kernel Image ... OK
OK
boot_prep_linux commandline: console=ttyS0,115200n8 maxcpus=1 mem=480M root=mtd3 rw rootfstype=jffs2
Starting kernel ...
INFO-Cygnus:471:start_kernel() entry
Booting Linux on physical CPU 0
Linux version 3.6.5-Broadcom Linux (bhsueh@bumblebee) (gcc version 4.7.2 (Broadcom Linux) ) #10 SMP Thu Mar 19 18:39:47
CST 2015
CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Broadcom iProc
cma: CMA: reserved 32 MiB at 7d000000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 7 pages/cpu @c09dc000 s6464 r8192 d14016 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 121920
Kernel command line: console=ttyS0,115200n8 maxcpus=1 mem=480M root=mtd3 rw rootfstype=jffs2
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 480MB = 480MB total
Memory: 448168k/448168k available, 43352k reserved, 0K highmem
Vi
rt
ual kernel memory layout:
ve
ctor : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xde800000 - 0xff000000 ( 520 MB)
lowmem : 0xc0000000 - 0xde000000 ( 480 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.text : 0xc0008000 - 0xc058c000 (5648 kB)
.init : 0xc058c000 - 0xc05ba940 ( 187 kB)
.data : 0xc05bc000 - 0xc05f2f20 ( 220 kB)
.bss : 0xc05f2f44 - 0xc0617954 ( 147 kB)
SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Hierarchical RCU implementation.
RC
U restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
NR_IRQS:292
arm-freq-id: 7
parent rate 25000000, x: 83886080
after shitf - current x: 2000000000
ARMPLL0: pdev: 1, ndev: 80, ndiv_frac: 0, mdiv: 4, rate: 2000000000
arm-freq-id: 7
arm-freq-id: 7
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
Calibrating delay loop... 1993.93 BogoMIPS (lpj=9969664)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x61468ff8 - 0x61469050
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c9, AUX_CTRL 0x0a130000, Cache size: 262144 B
Brought up 1 CPUs
SMP: Total of 1 processors activated (1993.93 BogoMIPS).
devtmpfs: initialized
NET: Registered protocol family 16
DMA: preallocated 16384 KiB pool for atomic coherent allocations
GENPLL[5] mdiv=40 rate=4000000000
UART clock rate 100000000
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource iproc_gtimer
NET: Registered protocol family 2
TCP established hash table entries: 16384 (order: 5, 131072 bytes)