ddr2时钟由pll1和pll2的最小值决定

The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum

throughput of the DDR2 bus. The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency

multiplied by 10. The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a

divide-by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller

of the two bus frequencies. For example, if the internal data bus frequency is 333 MHz (CPU frequency is

1 GHz) and the DDR2 bus frequency is 267 MHz (CLKIN2 frequency is 26.7 MHz), the maximum data

rate achievable by the DDR2 memory controller is 2.1 Gbytes/sec. The DDR2 bus is designed to sustain a

maximum throughput of up to 2.1 Gbytes/sec at a 533-MHz data rate (267-MHz clock rate), as long as

data requests are pending in the DDR2 Memory Controller.