杂七杂八2

1.设计完成后，如何判断一个成功的设计？
• 设计是否满足面积要求---是否能在选定的器件中实现； 通常资源占用率不要超过85%。
• 设计是否满足性能要求---能否达到要求的工作频率。
• 管脚定义是否满足要求---信号名、位置、电平标准及数 据流方向等。

2. 时序收敛：-通过对综合工具设置      -采用合适的优化技术      -修改布局布线
Locate Critical Paths? 

3. 使用SmartXplor.exploreAhead. 找到最佳综合策略。

4. Tcq：clock to q delay. Tsetup,Thold.Tsetup and Thold  specify the  time intervals before or after the sampling edge.
Maximal operating frequency: One of  the most difficult design aspects of  a sequential
circuit is  to ensure that the system  timing does not violate the setup and hold time constraints.

5.  Tclock = Tcp + Tcomp + Tsetup.  next-stage logic time. 组合电路延时
timing Constraints report: met?  

6. assign LED=1;

7. 综合报告。。。时序报告。

8. If you don't meet timing with this strategy, consider trying SmartXplorer.
9.ISE：

ISE : min,max,float,close.        View。
Toolbar!!!Find in files. Ctrl+Shift+F.
comment lines,selections.  Bookmark...
Find-mark all,
implement top module.?
Clean project Files.
 keep = true; 用户自定义模板 User templates.
10. The ISE Text Editor supports column selection for editing.
Design Goals & Strategies can be used to achieve your particular design goals by easily controlling implementation options
based on desired goals such as Power Reduction, Area Optimization, Runtime Reduction or Timing Performance
open examples.
To cover the data paths from the data pad to the first synchronous element, with respect to the clock pad to the same synchronous element, please use an OFFSET IN constraint.
增量编译SmartGuide:By default, the most recently implemented NCD file will be used as the guide file.
You may optionally specify any previously implemented NCD file as the guide file.

  Lay out-Load Default Layout.

11. Ensure the code is written optimally for critical paths 
 右键-Gene File-config rate。  更改设计方法，设计目标。Design Goals and strategies.
12. The Timing Closure User Guide (UG612)  PlanAhead User Guide (UG632)   Constraints Guide (UG625)

13. Verilog > Synthesis Constructs > Coding Examples > State Machines
14.  Embedded processor (XMP)

genvar <var>;
 generate
   for (<var>=0; <var> < <limit>; <var>=<var>+1)
   begin: <label>
   <instantiation>
   end
 endgenerate

15. (* PARALLEL_CASE *)来告诉综合器，不需要产生优先级逻辑，而缩小了硬件的规模。
16. 具有良好的代码风格
 Use synchronous design methodology
 Ensure the code is written optimally for critical paths
 Pipeline

17. 采用流水线：
always @(posedge clk)
begin
      e <= a+b+c;
      if(e ==d) 。。。
end

18. 要有两个思想：  用同步设计模式，用先组合后时序的模式。

19.   时钟驱动门，门打开，信号接入，变换！ 自动门。家门。
20. 所谓关键路径 ,我的理解就是时序情况最差的一些路径
静态时序分析报告里面会出来，之所以叫关键路径，是因为该路径上的延时直接影响到整个FPGA能够运行的最高频率，所以很关键。report
所谓关键路径就是，在电路中频繁调用，而且延迟过长，或者产生意外的几率比较大的线路。
通常情况下，考虑触发器到触发器之间的组合逻辑电路延时，如果组合逻辑电路之间的延时过大，就需要对组合逻辑拆分成若干个模块，模块之间再加入触发器，
这样就降低了原来组合逻辑电路的延时，满足电路的是需要求。
减少关键路径逻辑单元的个数。资源共享，
从项目开始到项目完成有许多路径，再整个网络图中最长的路径就叫关键路径。

21. Timing Analyzer可以读取时序报告，查找关键路径，并与Floorp
lanner协同解决时序问题

22. FPGA experts know if you want to improve your system spe
ed, first make sure you have evaluated the number of logic l
evels on your timing critical path

23. Verilog HDL代码优化技巧
资源共享：在互斥条件下共享ALU。 temp!!!
 if(sel) result = a  +  b; else result = a  +  c;
 reg [7:0]temp;
 if(sel) temp = b ; else temp =c;
 result = a+temp;
 当程序代码中存在互斥操作时，可以考虑是否对这些互斥操作进行资源共享。
r1 = a+b;r2 = r1+c;
资源共享-公共子表达式-代码调整-公因子。
将Dout的赋值改到组合逻辑中，则可以避免多余触发器的综合。
always语句块不能过多。尽量使用宏功能块。
Y = (a+b)+(c+d);
Y = a+b*c+d;-> Y = (a+d)+b*c;
b= 3*x; -> t=x<<1;b=x+t; 

24. a  Variable assigned in multiple always blocks. ---error：不能综合，组合！
b  Incomplete sensitivity list.      ---always @* warnning.
c  Incomplete branch and incomplete output assignment.
   Include all the branches of an if or case statement.
   Assign a value to every output signal in every branch.   ---use  default value

25.Guidelines
* Assign a variable only in a single always block.
* Use blocking statements for combinational circuits.
* Use @*  to include all  inputs automatically  in the sensitivity list.
* Make sure that all branches of the if and case statements are included.
* Make sure that the outputs are assigned in all branches.
* One way to satisfy the two previous guidelines is to assign default values for outputs
* in the beginning of the always block.
* Describe  the  desired  full case and parallel  case  in  code rather  than using  software
* directives or attributes.
* Be aware of the type of routing network inferred by different control constructs.
* Think hardware, not C code.

26.  a  large number  of items  in  a case statement  implies a
wide multiplexer, which makes synthesis difficult and  leads to a  large propagation delay.
5.1st stage,2nd stage,3rd stage...
The synchronous design methodology  is  the most commonly used practice in designing a sequential circuit.
In this methodology, all storage elements are controlled (i.e., synchronized) by a global clock
signal and the data is sampled and stored at the rising or falling edge of the clock signal.

27. TODO