CP15 协处理器 以及MCR MRC指令介绍
CP15 summary
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:
ARM9EJ-S Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
To control these features, CP15 provides 16 additional registers.
协处理器15，即统控制处理器 CP15，被用来配置和控制以下相关模块的功能支持：
ARM9EJ-S
Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
Notes:
1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field.
1.编号0-5 以及13，同样的编号不只代表一种寄存器。其中，寄存器的访问以来与opcode_2的值。
2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field.
2.同上，编号9的寄存器访问区分是依赖于CRm值。
2.CP15 Registers Access
CP15 registers can only be accessed in privileged mode by: MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.
MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register.
CP15寄存器只能通过下面2条指令进行访问操作：
MCR （从ARM寄存器写值到协处理器寄存器）指令方向 ARM REG --->CP15
MRC 反向与MCR相反
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
其它的诸如CDP LDC STC指令，会导致一个未定义的指令异常中断。
The assembler code for these instructions is:
汇编的代码格式如下：
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
指令的各部分参数功能如下：
CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior.
决定了协处理器的动作模式。它的值依赖于CP15的用途，细节参考CP15的特殊寄存器说明。
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
决定了协处理器的特殊操作代码。默认为0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
定义了，所要写入的ARM寄存器的编号。其中，该寄存器不能为PC（R15），否则结果是未知的。
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
目的协处理器编号
• L: Instruction Bit
0 = MCR instruction
1 = MRC instruction
指定了哪条指令
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
协处理器寄存器编号
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM.
更多细节参考TRM的第2章节。