fpga实现神经元

实现二输入逻辑与，逻辑或。没有用到乘法器，只用加法器和状态机，仿真没有问题，板子上运行还没有测试，仅供参考吧！

module perception(clk,en_start,en_train,data_in,rst_n,y_o,w_0);

input en_start;//神经元开始工作
input en_train;//是训练还是测试1训练，0测试
input clk;
input rst_n;//复位
input [3:0]data_in;
output y_o;//输出
output [12:0]w_0;
//reg [2:0]count_input;  //0 代表输入为0 0 1，    用case语句
    //1 代表输入为0 1 1，    实现net=w0*x1+w1*x2+w2*x3
    //2 代表输入为1 0 1，    x1、x2为输入，x3为偏置
    //3 代表输入为1 1 1，    w为参数




reg [2:0]ch_jud;  
//reg d_n;//参考值  
reg signed [12:0]net;  //神经元输入的和
reg o_n;//神经元的输出
reg signed [10:0]w00;//计算参数
reg signed [10:0]w01;
reg signed [10:0]w02;
reg signed [10:0]w10;//更新参数
reg signed [10:0]w11;
reg signed [10:0]w12;
//计数，控制计算状态
reg [4:0]state;
localparam IDLE=5'b00001,
NET_SUM=5'b00010,
JUDGE=5'b00100,
CHANGE=5'b01000,
UPDATE=5'b10000;
reg [10:0]ARF;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state=IDLE;
w00=11'b00010011000;
w01=11'b00011111100;
w02=11'b11101111000;
w10=11'b00010000000;
w11=11'b00010000000;
w12=11'b00010000000;
ARF=11'b00000110000;
net=13'd0;
o_n=1'b0;
end
else
begin
case(state)
IDLE:
begin
if(en_start==1'b1)
begin
state=NET_SUM;
w00=w00;
w01=w01;
w02=w02;
w10=w10;
w11=w11;
w12=w12;
net=net;
o_n=o_n;
end
else
begin
state=IDLE;
end
end
NET_SUM:
begin
case(data_in[3:1])//data_in为输入
3'b001:
net={w02[10],w02[10],w02};
3'b011:
net={w01[10],w01[10],w01}+{w02[10],w02[10],w02};
3'b101:
net={w00[10],w00[10],w00}+{w02[10],w02[10],w02};
3'b111:
net={w00[10],w00[10],w00}+{w01[10],w01[10],w01}+{w02[10],w02[10],w02};
default:
net=net;
endcase
state=JUDGE;
end
JUDGE:
begin
if(net>0)
o_n=1'b1;
else
o_n=1'b0;
if(en_train==1'b1)//为1训练，为0测试
begin
state=CHANGE;
end
else
begin
state=NET_SUM;
end
end
CHANGE:
begin

ch_jud={data_in[0],o_n,data_in[3]};//位拼接
case(ch_jud)
//sgn
3'b101:w10=w00+ARF;
3'b011:w10=w00-ARF;
//阶跃
//3'b101:w10=w00+{ARF[9:0],1'b0};//ARF*2
//3'b001:w10=w00-ARF;
//3'b011:w10=w00+ARF;
default:w10=w00;
endcase
ch_jud={data_in[0],o_n,data_in[2]};
case(ch_jud)
//sgn
3'b101:w11=w01+ARF;
3'b011:w11=w01-ARF;
//阶跃
//3'b101:w11=w01+{ARF[9:0],1'b0};//ARF*2
//3'b001:w11=w01-ARF;
//3'b011:w11=w01+ARF;
default:w11=w01;
endcase
ch_jud={data_in[0],o_n,data_in[1]};
case(ch_jud)
//sgn
3'b101:w12=w02+ARF;
3'b011:w12=w02-ARF;
//阶跃
//3'b101:w12=w02+{ARF[9:0],1'b0};//ARF*2
//3'b001:w12=w02-ARF;
//3'b011:w12=w02+ARF;
default:w12=w02;
endcase
state=UPDATE;
end
UPDATE:
begin
w00=w10;
w01=w11;
w02=w12;
state=NET_SUM;

//
end
default:
begin
//count_input=count_input;
w00=w00;
w01=w01;
w02=w02;
w10=w10;
w11=w11;
w12=w12;
net=net;
state=state;
end
endcase
end

end
assign y_o=o_n;
assign w_0=net;
endmodule