FPGA——UART串口通信2

设计要求

从PC的串口调试助手上发送32bit数据到FPGA，FPGA接收到数据以后把接收的数据返回给串口调试助手显示
115200bps，32bit

顶层架构

比特率产生模块和数据接收模块参考UART串口收发的原理与Verilog实现 代码

数据缓存模块

rxd_flag为数据接收模块数据接收完成信号，每一个8bit数据接收完成的同时，rxd_flag拉高，所以，在数据缓存模块，检测rxd_flag的下降沿作为缓存数据的标志，连续缓存4次，拼接为32bit数据

//接收4个8bit数据
	always @ (posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			begin
				done_flag    	<= 1'd0;
				para_data    	<= 32'd0;
				rxd_data_reg   <= 32'd0;
				state        	<= 4'd0;
			end
		else
			case(state)
				4'd0:
					begin
						done_flag   	 <= 1'd0;
						para_data       <= para_data;
						rxd_data_reg    <= 32'd0;
						state           <= state + 1'd1;	
					end
				4'd1:
					begin
						if(rxd_flag_neg)
							begin
								rxd_data_reg[7:0] <= rxd_data;
								state           	<= state + 1'd1;
							end
						else
							state <= state;
					end
				4'd2:
					begin
						if(rxd_flag_neg)
							begin
								rxd_data_reg[15:8] <= rxd_data;
								state            	 <= state + 1'd1;
							end
						else
							state <= state;
					end
				4'd3:
					begin
						if(rxd_flag_neg)
							begin
								rxd_data_reg[23:16] <= rxd_data;
								state               <= state + 1'd1;
							end
						else
							state <= state;
					end
				4'd4:
					begin
						if(rxd_flag_neg)
							begin
								rxd_data_reg[31:24] <= rxd_data;
								state           	  <= state + 1'd1;
							end
						else
							state <= state;
					end
				4'd5:
					begin
						para_data <= rxd_data_reg;
						done_flag <= 1;
						state 	 <= 0;
					end
				endcase
	end 

发送数据模块

检测uart_tx_en信号，若其为高，则进入数据发送状态，准备发送数据。
按照数据协议，起始位发0，结束位发1，中间发送数据，连续发送四次，组要40个时钟周期

// 发送数据状态机
	always @(posedge clk or negedge rst_n)
	begin
		 if(!rst_n)
			begin
				uart_tx_cke <= 1'd0;
				R_state 		<=T_IDLE;
				cnt         <= 6'd0;
			end
		else
			case(R_state)
				T_IDLE:
					begin
						if(R_transmiting)
							begin
								uart_tx_cke <= 1'd1 ;
								R_state <= T_SEND;
							end
						else	
							begin
								R_state 		<=	T_IDLE;
								uart_tx_cke <= 1'd0;
								
							end
					end
				T_SEND:
					begin
						if(uart_tx_clk)
							begin
								if(cnt < 6'd40)
									begin
										cnt 		<= cnt + 1'd1;
										R_state 	<= T_SEND;
									end
								else
									begin
										cnt 	  <= 6'd0;
										R_state <= T_IDLE;
									end
							end
						else
							begin
								cnt <= cnt;
								R_state <= R_state;
							end
					end
			endcase
	end
			
	always @ (*)
		begin
			if(R_state == T_SEND)
				case(cnt)
					6'd1:	txd = 0 ;// 发送起始位
					6'd2: txd = txd_data[0];//发送0-7bit
					6'd3: txd = txd_data[1];
					6'd4: txd = txd_data[2];
					6'd5: txd = txd_data[3];
					6'd6: txd = txd_data[4];
					6'd7: txd = txd_data[5];
					6'd8: txd = txd_data[6];
					6'd9: txd = txd_data[7];
					6'd10: txd = 1;//发送停止位
					
					6'd11:txd = 0;// 发送起始位
					6'd12:txd = txd_data[8];//发送8-15bit
					6'd13:txd = txd_data[9];
					6'd14:txd = txd_data[10];
					6'd15:txd = txd_data[11];
					6'd16:txd = txd_data[12];
					6'd17:txd = txd_data[13];
					6'd18:txd = txd_data[14];
					6'd19:txd = txd_data[15];
					6'd20:txd = 1;//发送停止位
					
					6'd21:txd = 0;// 发送起始位
					6'd22:txd = txd_data[16];//发送16-23bit
					6'd23:txd = txd_data[17];
					6'd24:txd = txd_data[18];
					6'd25:txd = txd_data[19];
					6'd26:txd = txd_data[20];
					6'd27:txd = txd_data[21];
					6'd28:txd = txd_data[22];
					6'd29:txd = txd_data[23];
					6'd30:txd = 1;//发送停止位
					
					6'd31:txd = 0;// 发送起始位
					6'd32:txd = txd_data[24];//发送24-31bit
					6'd33:txd = txd_data[25];
					6'd34:txd = txd_data[26];
					6'd35:txd = txd_data[27];
					6'd36:txd = txd_data[28];
					6'd37:txd = txd_data[29];
					6'd38:txd = txd_data[30];
					6'd39:txd = txd_data[31];
					6'd40:txd = 1;//发送停止位
					default:txd=1;
				endcase
			else
				txd = 1'b1;
		end
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		txd_flag <= 0;
	else if(uart_tx_clk == 1 &&  cnt == 6'd39 )
		txd_flag <= 1;
	else
		txd_flag <= 0;
end