vivado的简单使用
15/9/12
使用vivado的RTL Analysis可以查看生成电路图且器件必须set as top
使用ctrl+a/t可以按列选择文本
error
[Synth 8-3966] non-net port in cannot be of mode input: `default_nettype is "none" ["……/YM38.v":25]
input 是不能使用reg 这种定义的
在 always @（）里面使用模块是无效的
错误案例：
always @( num or node )
begin
if(select)
//共阳极
smg_a a(.num(num),.node(node),.CX(CX));
else
//共阴极
smg_c c(.num(num),.node(node),.CX(CX));
end
begin end 作用等同于括号
[HDL 9-806] Syntax error near "else".
错误案例:
if(select)
//共阳极
num_a <= num;
num_c <= 4'bzzzz;
else
//共阴极
num_c <= num;
num_a <= 4'bzzzz;
正确使用：
always @( num )
begin
if(select)
begin//共阳极
num_a <= num;
num_c <= 4'bzzzz;
end
else
begin//共阴极
num_c <= num;
num_a <= 4'bzzzz;
end
end
如果Add Design Source那么文件会保存在import里，即使你的是从自己项目里import的
如果生成比特流时报错管脚约束有问题，那就重新检查管脚约束
报错：
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] >
reset_IBUF_inst (IBUF.O) is locked to IOB_X1Y66
and reset_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
问题段：
reg point = 1'b1 ;
smg U3(.clock(clock),.num(num),.point(point),.select(sw[3]),.cm(sw[2]),.CX(out_smgC));
always @ ( reset )
begin
if( reset )
point = ~point;
else
end
这种问题是因为：
从外部来的（接到板子上的）always语句中的敏感信号为时钟以外的外部信号，因为Vivado在处理外部时钟信号的时候会自动添加BUFG模块来去除时钟的抖动，但是其他的信号就不会这样做，这样的话在always语句的敏感信号列表中使用没有去抖动的外部信号就有可能导致系统不稳定，所以会出现这个错误。
需要在IO配置文件最后添加：set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF]