串口通信USART Top程序以及Tectbench程序

使用Verilog代码编写的自收自发的顶层程序：

module uart_top(clk,reset,enable,RX,TX,testp);
input clk,reset,enable;
input RX;
output TX;
output [7:0]testp;

wire [7:0]data;
wire RxOK;
//wire TxAv;//发送有效
wire TxOK;

//RxOK:tx_en:__/^\____________________
//tx_idle:_____________________/^\____
//TxAv:________/^^^^^^^^^^^^^^^\_______
/*  产生采样时钟,产生波特率clk_bps  */
SpeedSet S1(.clk(clk),.reset(reset),.cnt(clk_bps));
uart_recv R1(.GClk(clk),.clk_bps(clk_bps),.reset(reset),.rx_en(enable),.Rxd(RX),.datain(data),.rx_ok(RxOK));
uart_trans T1(.GClk(clk),.clk_bps(clk_bps),.reset(reset),.tx_en(RxOK),.datain(data),.Txd(TX),.tx_ok(TxOK),.test(testp));
endmodule

使用VHDL语言编写的Testbench程序：

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   23:33:36 11/19/2015
-- Design Name:   
-- Module Name:   
-- Project Name:  Uart
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: uart_top
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY uart_tsb IS
END uart_tsb;
 
ARCHITECTURE behavior OF uart_tsb IS 
 
constant bps9600:integer :=5208;
constant bps9600_2:integer :=2604;
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT uart_top
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         enable : IN  std_logic;
         RX : IN  std_logic;
         TX : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal enable : std_logic := '0';
   signal RX : std_logic;
 	--Outputs
   signal TXD : std_logic;
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
signal clk_2:std_logic:='0';
signal sample:integer range 0 to 10240:=0;
signal cnt:integer range 0 to 10240:=0;
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: uart_top PORT MAP (
          clk => clk,
          reset => reset,
          enable => enable,
          RX => RX,
          TX => TXD
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
process(clk,reset)
begin
	if reset='0' then
		sample<=10;
		clk_2<='0';
	elsif (clk'event and clk='1') then
		if(sample=bps9600) then
			sample <= 0;
			clk_2 <= '1';
		else
			sample <= sample + 1;
			if(sample=bps9600_2) then
				clk_2 <= '0';
			end if;
		end if;
	end if;
end process;

process(clk_2,reset)
begin
	if(reset='0') then
		cnt<=0;
	elsif (clk_2'event and clk_2='1') then
		cnt <= cnt + 1;
	end if;
end process;

process(clk_2,cnt,reset)
begin
	if reset='0' then
		RX<='1';
	elsif (clk_2'event and clk_2='1') then
		case(cnt) is
			when 1 => RX <= '0';
			when 2 => RX <= '1';
			when 3 => RX <= '0';
			when 4 => RX <= '1';
			when 5 => RX <= '0';
			when 6 => RX <= '1';
			when 7 => RX <= '1';
			when 8 => RX <= '0';
			when 9 => RX <= '0';
			when 10 => RX <= '1';
			when 11 => RX <= '1';
			when 12 => RX <= '1';
			when 13 => RX <= '0';
			when 14 => RX <= '1';
			when 15 => RX <= '1';
			when 16 => RX <= '1';
			when 17 => RX <= '1';
			when 18 => RX <= '1';
			when 19 => RX <= '1';
			when 20 => RX <= '1';
			when 21 => RX <= '0';
			when 22 => RX <= '1';
			when others => RX <= '1';
		end case; 
	end if;
end process;

   -- Stimulus process
   stim_proc: process
   begin		
		reset <= '0';
		enable <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		reset <= '1';
      wait for clk_period*10;
      -- insert stimulus here 
      wait;
   end process;
END;

最终附上Modelsim仿真图：