宣&模板

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library ieee; --库函数

use ieee.std_logic_1164.all;--定义了std_logic数据类型及相应运算

entity exp1 is

port(

clk:in bit;

display:out  STD_logic_VECTOR(7 DOWNTO 0);

position:out STD_logic_VECTOR(2 DOWNTO 0)

);

end exp1;

architecture V1 of exp1 is

type port_state is(d0,d1,d2,d3,d4,d5,d6,d7);

signal state:port_state;

begin

process(clk)

begin

if(clk'event and clk='1')then

case state is

when d0 =>position<="000"; display <="00000000";state<=d1;

when d1 =>position<="001"; display <="00000000";state<=d2;

when d2 =>position<="010"; display <="00000000";state<=d3;

when d3 =>position<="011"; display <="00000000";state<=d4;

when d4 =>position<="100"; display <="00000000";state<=d5;

when d5 =>position<="101"; display <="01100110";state<=d6;

when d6 =>position<="110"; display <="11111101";state<=d7;

when d7 =>position<="111"; display <="11110111";state<=d0;

end case;

end if;

end process;

end V1;