乘法器（流水线结构） Verilog HDL

乘法器（流水线结构） Verilog HDL

RTL代码：

module mul(
clk,
rstn,
a,
b,
result
);


input clk;
input rstn;
input [15:0] a;
input [15:0] b;

output reg [31:0] result;


reg [15:0]a0,a1,a2,a3,a4,a5,a7,a6,a8,a9,a10,a11,
          a12,a13,a14,a15;
reg   [31:0]   add01  ,			 
               add23  ,
               add45  ,
               add67  ,
               add89  ,			 
               add1011,			 
               add1213,			 
               add1415;	

reg   [31:0]   ad01  ,			 
               ad23  ,
               ad45  ,
               ad67  ;

reg   [31:0]   a01  ,			 
               a23  ;
		 
			 
always@(posedge clk)
  if(!rstn)
     begin
	  a0   <=16'd0;
	  a1   <=16'd0;
	  a2   <=16'd0; 
	  a3   <=16'd0; 
	  a4   <=16'd0;  
	  a5   <=16'd0;
	  a6   <=16'd0;
	  a7   <=16'd0;
	  a8   <=16'd0;
	  a9   <=16'd0;
	  a10  <=16'd0;
	  a11  <=16'd0;
	  a12  <=16'd0;
	  a13  <=16'd0;
	  a14  <=16'd0;
	  a15  <=16'd0;
	  end
  else
     begin
	  a0   <=b[0] ?a:16'd0;
	  a1   <=b[1] ?a:16'd0;
	  a2   <=b[2] ?a:16'd0; 
	  a3   <=b[3] ?a:16'd0; 
	  a4   <=b[4] ?a:16'd0;  
	  a5   <=b[5] ?a:16'd0;
	  a6   <=b[6] ?a:16'd0;
	  a7   <=b[7] ?a:16'd0;
	  a8   <=b[8] ?a:16'd0;
	  a9   <=b[9] ?a:16'd0;
	  a10  <=b[10]?a:16'd0;
	  a11  <=b[11]?a:16'd0;
	  a12  <=b[12]?a:16'd0;
	  a13  <=b[13]?a:16'd0;
	  a14  <=b[14]?a:16'd0;
	  a15  <=b[15]?a:16'd0;
	  end
	   
	
always@(posedge clk)
   if(!rstn)
     begin
	   add01 <=32'd0;
		add23 <=32'd0;
		add45 <=32'd0;
		add67 <=32'd0;
		add89 <=32'd0;
		add1011 <=32'd0;
		add1213 <=32'd0;
		add1415 <=32'd0;
	  end 
	else
	  begin
	   add01   <={16'b0,a0}+{15'b0,a1,1'b0};
		add23   <={14'b0,a2,2'b0}+{13'b0,a3,3'b0};
		add45   <={12'b0,a4,4'b0}+{11'b0,a5,5'b0};
		add67   <={10'b0,a6,6'b0}+{9'b0,a7,7'b0};
		add89   <={8'b0,a8,8'b0}+{7'b0,a9,9'b0};
		add1011 <={6'b0,a10,10'b0}+{5'b0,a11,11'b0};
		add1213 <={4'b0,a12,12'b0}+{3'b0,a13,13'b0};
		add1415 <={2'b0,a14,14'b0}+{1'b0,a15,15'b0};
	  end
	 
always@(posedge clk)
  if(!rstn)
   begin
   ad01 <=32'd0;
	ad23 <=32'd0;
	ad45 <=32'd0;
   ad67 <=32'd0;
   end
  else
   begin
   ad01 <=add01+add23;
	ad23 <=add45+add67;
	ad45 <=add89+add1011;
	ad67 <=add1213+add1415;
	end

always@(posedge clk)
   if(!rstn)
      begin
	   a01 <=32'd0;
	   a23 <=32'd0;
      end	
	else
	  begin
	   a01 <=ad01 +ad23;
	   a23 <=ad45 + ad67;
	  end
		
always@(posedge clk)
   if(!rstn)
	   result <=32'd0;
	else
	   result <=a01 +a23;
	
endmodule 

测试激励：

module mul_tb();

reg clk;
reg rstn;
reg [15:0] a;
reg [15:0] b;

wire [31:0] result;

mul mul(
    .clk(clk),
    .rstn(rstn),
    .a(a),
    .b(b),
    .result(result)
);

always #5 clk =~clk;

initial
       begin
		      clk=0;
				#3 rstn=0;
				   a=16'habcd;
					b=16'hef79;
				#(10) rstn=1;
			#(100) $stop;
		 
		 end


endmodule