FPGA之流水线算法实现八位加法器

1.普通方法实现八位加法器

/*******************8位加法器(非流水线)***********************/
module adder_nonpipe(cout, sum, ina, inb, cin, enable);

output cout;
output [7:0] sum;
input [7:0] ina, inb;
input cin, enable;

reg cout;
reg [7:0] sum;
reg [7:0] tempa, tempb;
reg tempc;

always @(posedge enable)
begin
    tempa = ina;
    tempb = inb;
    tempc = cin;
end

always @(posedge enable)
begin
    {cout,sum} = tempa + tempb + tempc;
end

endmodule

2.流水线方法实现八位加法器

/*******************8位2级流水加法器*************************/
module adder_pipeline(cout, sum, ina, inb, cin, enable);

output cout;
output [7:0] sum;
input [7:0] ina, inb;
input cin, enable;

reg cout;
reg [7:0] sum;

reg [3:0] tempa, tempb, firsts;
reg firstc;
always @(posedge enable)
begin
    {firstc,firsts} = ina[3:0] + inb[3:0] + cin;
    tempa = ina[7:4];        //高4位输入寄存，使其与sum低4位在下级流水线同步输入。
       tempb = inb[7:4];        //否则sum的高4位，与低四位分两个时钟周期输出
end

always @(posedge enable)
begin
    {cout,sum[7:4]} = tempa + tempb + firstc;
    sum[3:0] = firsts;       //不能合并为{cout, sum} = {tempa + tempb + firstc, firsts}; 位宽不匹配
end

endmodule