单脉冲采样（1）---慢时钟采样快时钟

pulse_sample

适用场景

适用于脉冲信号采样，慢时钟采样快时钟

基本原理

将快时钟域的脉冲信号扩展成多周期的电平信号，慢时钟同步电平信号进行采样得到同步后的电平信号，此时通过电平延时组合逻辑由电平产生脉冲信号。

限制

快时钟域的两次脉冲应该应该有一定的间隔，否则扩展后的电平信号连在一起了，会导致同步后的信号只有一个脉冲

说明

源时钟域src_pulse依次输入给src_pulse_seq[0]、src_pulse_seq[1]、src_pulse_seq[2]，四个信号相或产生的信号输入给寄存器src_pulse_extend。寄存器src_pulse_extend通过两级同步打拍得到sync_temp,sync_temp依次打拍得到src_pulse_expand_delay1、src_pulse_expand_delay2。再由(src_pulse_expand_delay1)&&(!src_pulse_expand_delay2)得到脉冲信号dst_pulse_tmp，dst_pulse_tmp打拍得到目的时钟域脉冲dst_pulse。

verilog

module pulse_sample(
        // source clock domain signals
        src_clk,
  src_async_rst_n,
  src_pulse,
  // dst  clock domain signals
  dst_clk,
  dst_async_rst_n,
  dst_pulse
  );
 
 parameter                       EXTEND_NUM = 4;
 // source clock domain signals
 input                           src_clk;
 input                           src_async_rst_n;
 input                           src_pulse;
 // dst  clock domain signals
 input                           dst_clk;
 input                           dst_async_rst_n;
 output                          dst_pulse;
 
 reg    [EXTEND_NUM-2:0]         src_pulse_seq;
 reg                             src_pulse_extended;
 reg                             sync_temp;
 
 reg                             src_pulse_sync;
 reg                             src_pulse_expand_delay1;
 reg                             src_pulse_expand_delay2;
 reg                             dst_pulse;
 wire                            dst_pulse_tmp;
 
 always@(posedge src_clk or negedge src_async_rst_n)
     if(!src_async_rst_n)
  begin
      src_pulse_seq[EXTEND_NUM-2:0]      <= {(EXTEND_NUM-1){1'b0}};
     src_pulse_extended                 <= 1'b0;
  end
  else
  begin
      src_pulse_seq[0]                   <= src_pulse;
      src_pulse_seq[EXTEND_NUM-2:1]      <= src_pulse_seq[EXTEND_NUM-3:0];
     src_pulse_extended                 <= src_pulse|(|(src_pulse_seq[EXTEND_NUM-2:0]));
  end
  
 always@(posedge dst_clk or negedge dst_async_rst_n)
        if(!dst_async_rst_n)
     begin
       sync_temp        <= 1'b0;
      src_pulse_sync   <= 1'b0;
     end
     else
     begin
       sync_temp        <= src_pulse_extended;
      src_pulse_sync   <= sync_temp;
     end
    
 assign dst_pulse_tmp  =   (src_pulse_expand_delay1)&&(!src_pulse_expand_delay2);
   
 always@(posedge dst_clk or negedge dst_async_rst_n)
        if(!dst_async_rst_n)
     begin
       src_pulse_expand_delay1    <= 1'b0;
      src_pulse_expand_delay2    <= 1'b0;
      dst_pulse                  <= 1'b0;
      end
     else
     begin
       src_pulse_expand_delay1    <= src_pulse_sync           ;
      src_pulse_expand_delay2    <= src_pulse_expand_delay1  ;
      dst_pulse                  <= dst_pulse_tmp            ;
     end
    endmodule