VHDL 加法器

-用结构方法设计一个半加器。两个一位二进制数Ai 和Bi相加，Si为半加器的和，Si+1为进位输出。
--第一步设计低层实体:xor_gate	 
Library  ieee;
Use  ieee.std_logic_1164.all;
Entity  xor_gate is
Port(
	Op1 :in std_logic;
	Op2 :in std_logic ;
 	Xor_result :out std_logic);
End xor_gate;
Architecture behave of xor_gate is
	Begin
		Xor_result<=Op1 and Op2;
End behave;
Library  ieee;
Use  ieee.std_logic_1164.all;

Entity and_gate is
	Port(
  Op1 :in std_logic;
	Op2 :in std_logic ;
 	and_result :out std_logic);
End and_gate;
Architecture behave1 of and_gate is
	begin 
         and_result<=op1 and op2;
end behave1;
--第二步设计顶层实体
Library  ieee;
Use  ieee.std_logic_1164.all;
Entity  Halfadder  is
Port(
	Ai :in std_logic ;
	Bi :in std_logic;
	Si: out std_logic;
	Ci+1:out std_logic );
End Halfadder;
Architecture struct of Halfadder is
	Component xor_gate
		Port(
			Op1:in std_logic;
			Op2:in std_logic;
			Xor_result:out std_logic);
	End Component;
	Component and_gate
        Port(
	Op1:in std_logic;
	Op2:in std logic;
	And_result:out std_logic);
End component;

	Begin 
		G1:Xor_gate port map  --对异或门xor_gate进行第一次例化
			(
Op1=>Ai,
Op2=>Bi,
Xor_result=>Si);
		G2:and_gate port map   --对异或门xor_gate进行第二次例化
			(
Op1=>Ai,
Op2=>Bi,
And_result=>Ci+1);
   	End struct;