modlesim 仿真流程

1.编写verilog文件

module adder4(cout,sum,ina,inb,cin); //4位加法器

output[3:0] sum;

output cout;

input[3:0] ina,inb;

input cin;

assign {cout,sum}=ina+inb+cin;

endmodule

--------

module count4(out,reset,clk); //4位计数器

output[3:0]  out;

input reset,clk;

reg[3:0] out;

always @(posedge clk)

begin

if (reset) out<=0;

else out<=out+1;

end

endmodule

2.编写测试文件：

adder_tp.v

`timescale 1ns/1ns

`include "adder4.v"

module adder_tp;

reg[3:0] a,b;

reg cin;

wire[3:0] sum;

wire cout;

integer i,j;

adder4 adder(sum,cout,a,b,cin);

always #5 cin=~cin;

initial

begin

a=0;b=0;cin=0;

for(i=1;i<16;i=i+1)

#10 a=i;

end

initial

begin

for(j=1;j<16;j=j+1)

#10 b=j;

end

initial

begin

$monitor($time,,,"%d+%d+%b={%b,%d}",a,b,cin,cout,sum);

#160 $finish;

end

endmodule

3.执行编译

4.在library库中对测试文件执行仿真

5.查看波形图