NVM Express 1.2.1
1.4.1 Multi-Path I/O and Namespace Sharing
1.4.1 多路IO和命名空间共享
This section provides an overview of multi-path I/O and namespace sharing. Multi-path I/O refers to two or more completely independent PCI Express paths between a single host and a namespace while namespace sharing refers to the ability for two or more hosts to access a common shared namespace using different NVM Express controllers. Both multi-path I/O and namespace sharing require that the NVM subsystem contain two or more controllers. Concurrent access to a shared namespace by two or more hosts requires some form of coordination between hosts. The procedure used to coordinate these hosts is outside the scope of this specification.
这一节将对多路I/O和命名空间共享做一个概述。多路I/O指的是存在于单个主机和命名空间之间的N(>=2)个完全独立的PCIe通道。命名空间共享则是指N(>=2)个主机使用不同的NVMe控制器访问同一个共享空间的能力。无论是多路I/O还是命名空间共享，都需要NVM子系统包含N(>=2)个控制器。并发访问共享的命名空间,需要在多个(>=2)主机之间做某种形式的协调。如何在这些主机做协调，不在本技术规范的讨论范围之内。
Figure 3 shows an NVM subsystem that contains a single NVM Express controller and a single PCI Express port. Since this is a single Function PCI Express device, the NVM Express controller shall be associated with PCI Function 0. A controller may support multiple namespaces. The controller in Figure 3 supports two namespaces labeled NS A and NS B. Associated with each controller namespace is a namespace ID, labeled as NSID 1 and NSID 2, that is used by the controller to reference a specific namespace. The namespace ID is distinct from the namespace itself and is the handle a host and controller use to specify a particular namespace in a command. The mapping of a controller's namespace IDs to namespaces is outside the scope of this specification. In this example namespace ID 1 is associated with namespace A and namespace ID 2 is associated with namespace B. Both namespaces are private to the controller and this configuration supports neither multi-path I/O nor namespace sharing.
图3中的NVM子系统包含了一个单一的NVMe控制器和一个PCIe端口。由于这是一个单一功能的PCIe设备，NVMe控制器必然与PCI Function 0相关联。一个控制器可以支持多个命名空间。图3中的控制器支持两个命名空间，NS A和 NS B。与每一个控制器命名空间相关联的是命名空间ID，标记为NSID 1和NSID 2，控制器通过这些ID来引用特定的命名空间。命名空间ID是与命名空间本身是独立的，它是主机及控制器用来在命令中指定特定的命名空间的句柄。如何将控制器命名空间ID映射到命名空间则超出了本规范的讨论范围。在这个例子中，命名空间ID1与命名空间 A相关联，命名空间ID2则与命名空间B相关联。两个命名空间对控制器来说都是私有的，这一配置既不支持多路I/O，也不支持命名空间共享。
Figure 4 shows a multi-Function NVM Subsystem with a single PCI Express port containing two controllers, one controller is associated with PCI Function 0 and the other controller is associated with PCI Function 1. Each controller supports a single private namespace and access to shared namespace B. The namespace ID shall be the same in all controllers that have access to a particular shared namespace. In this example both controllers use namespace ID 2 to access shared namespace B.
在图4中，具有一个PCIEe端口的多Function的NVM子系统包含了两个控制器。其中，一个控制器与PCI Function 0相关联，另一个控制器与PCI Function 1相关联。每一个控制器支持一个私有的命名空间，同时能够访问共享的命名空间B。对所有能够访问特定的共享命名空间的所有控制器来说，命名空间ID必然是相同的。在这个例子中，两个控制器均使用命名空间ID2去访问共享的命名空间B。
There is a unique Identify Controller data structure for each controller and a unique Identify Namespace data structure for each namespace. Controllers with access to a shared namespace return the Identify Namespace data structure associated with that shared namespace (i.e., the same data structure contents are returned by all controllers with access to the same shared namespace). There is a globally unique identifier associated with the namespace itself and may be used to determine when there are multiple paths to the same shared namespace. Refer to section 7.10.
每个控制器都有一个唯一标识的控制器数据结构，每个命名空间都有一个唯一标识的命名空间数据结构。访问共享命名空间的控制器返回与该共享命名空间相关联的标识命名空间数据结构(也就是说，所有访问同一个共享命名空间的控制器返回相同的数据结构内容)。与命名空间本身相关联的标识符是全局唯一的，它可用来确定同一个命名空间，当存在多个通路能够访问该共享的命名空间的时候。具体的请参见7.10一节。
Controllers associated with a shared namespace may operate on the namespace concurrently. Operations performed by individual controllers are atomic to the shared namespace at the write atomicity level of the controller to which the command was submitted (refer to section 6.3). The write atomicity level is not required to be the same across controllers that share a namespace. If there are any ordering requirements between commands issued to different controllers that access a shared namespace, then host software or an associated application, is required to enforce these ordering requirements.
与某个共享的命名空间相关联的控制器们可以同时操作该命名空间。命令提交给控制器，不同的控制器执行的操作对共享命名空间来说是写原子级的(请参见6.3节)。如果访问某个共享的命名空间的控制器是相同的，那么写原子操作就不是必须的。如果向不同的控制器发出的命令之间在访问共享命名空间有任何有序化的要求的话，主机软件或相关应用程序必须执行这些命令的有序化要求。
Figure 5 illustrates an NVM Subsystem with two PCI Express ports, each with an associated controller. Both controllers map to PCI Function 0 of the corresponding port. Each PCI Express port in this example is completely independent and has its own PCI Express Fundamental Reset and reference clock input. A reset of a port only affects the controller associated with that port and has no impact on the other controller, shared namespace, or operations performed by the other controller on the shared namespace. The functional behavior of this example is otherwise the same as that illustrated in Figure 4.
图5中的NVM子系统中有两个PCIe端口，每一个端口关联一个控制器。每一个控制器将端口映射到PCI Function 0。在这个例子中，每一个PCIe端口都是完全独立的，都有它自己的PCIe基座复位和参照时钟输入。端口的复位仅仅影响与该端口相关联的控制器，对其他控制器、共享命名空间或由共享命名空间上的其他控制器执行的操作没有任何影响。要不然的话，这一示例的功能行为与图4所示的功能行为是相同的。
The two ports shown in Figure 5 may be associated with the same Root Complex or with different Root Complexes and may be used to implement both multi-path I/O and I/O sharing architectures. System-level architectural aspects and use of multiple ports in a PCI Express fabric are beyond the scope of this specification.
图5所示的两个端口可能与同一个RC相关联，也可能与不同的RC相关联，可既用来实现多路I/O架构，也实现共享I/O架构。有关系统级架构和在PCIe fabric中使用多个端口,不在本技术规范讨论的范围之内。
Figure 6 illustrates an NVM Subsystem that supports Single Root I/O Virtualization (SR-IOV) and has one Physical Function and four Virtual Functions. An NVM Express controller is associated with each Virtual Function with each controller having a private namespace and access to a namespace shared by all controllers, labeled NS E. The behavior of the controllers in this example parallels that of the other examples in this section. Refer to section 8.5 for more information on SR-IOV.
在图6中的一个NVM子系统支持SR-IOV，拥有1个PF和4个VF。 每个VF关联一个NVMe控制器，每个控制器都有私有的命名空间，同时能够访问共享的命名空间NS E。在这个例子中，控制器的行为与本节中的其他示例类似。有关SR-IOV的更多信息请参见8.5节。
Examples provided in this section are meant to illustrate concepts and are not intended to enumerate all possible configurations. For example, an NVM subsystem may contain multiple PCI Express ports with each port supporting SR-IOV.
这一节中提供的例子旨在阐明概念，而不是枚举所有可能的配置。例如，一个NVMe子系统可能包含多个PCIe端口，每个端口都支持SR-IOV。
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