VHDL实现4线-16线译码器

源代码：

library ieee;
use ieee.std_logic_1164.all;

entity decoder4_16 is
	port(i: in std_logic_vector(3 downto 0);
		y: out std_logic_vector(15 downto 0));
end decoder4_16;

architecture func of decoder4_16 is
begin 
	process(i)
	begin
	y <= "0000000000000000";
	case i is
	when "0000" => y(0) <= '1';
	when "0001" => y(1) <= '1';
	when "0010" => y(2) <= '1';
	when "0011" => y(3) <= '1';
	when "0100" => y(4) <= '1';
	when "0101" => y(5) <= '1';
	when "0110" => y(6) <= '1';
	when "0111" => y(7) <= '1';
	when "1000" => y(8) <= '1';
	when "1001" => y(9) <= '1';
	when "1010" => y(10) <= '1';
	when "1011" => y(11) <= '1';
	when "1100" => y(12) <= '1';
	when "1101" => y(13) <= '1';
	when "1110" => y(14) <= '1';
	when "1111" => y(15) <= '1';
	when others => y <= "0000000000000000";
	end case;
	end process;
end architecture;

功能仿真：