DC 在Compile 时出错退出，不知道怎么解决

design_vision-topo> compile_ultra
Information: Performing power optimization. (PWR-850)
Alib files are up-to-date.
Error: Layer METAL does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Layer METAL2 does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Layer METAL3 does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Layer METAL4 does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Layer METAL5 does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Layer METAL6 does not have preferred routing direction defined, neither in the design(CEL) nor in the library. (PSYN-486)
Error: Routing layers sanity check failed. (OPT-1430)
Warning: Some checks cannot be performed because of previous errors. (DCT-006)
0
design_vision-topo> set_preferred_routing_direction -layers {METAL METAL3 METAL5} -direction horizontal
Warning: Not all metal layers have preferred routing direction. (OPT-1427)
1
design_vision-topo> set_preferred_routing_direction -layers {METAL2 METAL4 METAL6} -direction vertical
1
design_vision-topo> compile_ultra
Information: Performing power optimization. (PWR-850)
Alib files are up-to-date.
Error: The target library does not contain all required gates.
Either a NOR, or an AND and an OR gate (two-input) is required for mapping. (OPT-102)
Loading db file '/opt/Synopsys/Synplify2015/libraries/syn/dw_foundation.sldb'
Warning: DesignWare synthetic library dw_foundation.sldb is added to the synthetic_library in the current command. (UISN-40)
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | K-2015.06-DWBB_201506.0 |     *     |
| Licensed DW Building Blocks        | K-2015.06-DWBB_201506.0 |     *     |
| fast                               | 1.300000                |           |
| fast_leakage                       | 1.300000                |           |
| fastz                              | 1.300000                |           |
| slow                               | 1.300000                |           |
| typical                            | 1.300000                |           |
| typical_leakage                    | 1.300000                |           |
============================================================================

Information: Sequential output inversion is enabled.  SVF file must be used for formal verification. (OPT-1208)

  Loading target library 'cb13fs120_tsmc_max'
Error: The target library does not contain all required gates.
Either a NOR, or an AND and an OR gate (two-input) is required for mapping. (OPT-102)
Error: Compile has abnormally terminated.  (OPT-100)
[IC@IC lab1]$