uvm实战例子2.2.4(linux+vcs)

测试文件dut

module dut(clk,
           rst_n, 
           rxd,
           rx_dv,
           txd,
           tx_en);
input clk;
input rst_n;
input[7:0] rxd;
input rx_dv;
output [7:0] txd;
output tx_en;

reg[7:0] txd;
reg tx_en;

always @(posedge clk) begin
   if(!rst_n) begin
      txd <= 8'b0;
      tx_en <= 1'b0;
   end
   else begin
      txd <= rxd;
      tx_en <= rx_dv;
   end
end
endmodule

my_driver

`ifndef MY_DRIVER__SV
`define MY_DRIVER__SV
class my_driver extends uvm_driver;
  virtual my_if vif;
  `uvm_component_utils(my_driver);
  function new(string name = "my_driver", uvm_component parent = null);
    super.new(name, parent);
    `uvm_info("my_driver", "new is called", UVM_LOW);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("my_driver", "build_phase is called", UVM_LOW);
    if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
      `uvm_fatal("my_driver", "virtual interface must be set for vif!!!");
  endfunction
  extern virtual task main_phase(uvm_phase phase);
endclass

task my_driver::main_phase(uvm_phase phase);
  phase.raise_objection(this);
  `uvm_info("my_driver","main_phase is called",UVM_LOW);
  vif.data<=8'b0;
  vif.valid<=1'b0;
  while(!vif.rst_n)
    @(posedge vif.clk);
  for(int i;i<256;i++)begin
    @(posedge vif.clk);
    vif.data<=$urandom_range(0, 255);
    vif.valid<=1'b1;
    `uvm_info("my_driver","data is drived",UVM_LOW);
  end
  @(posedge vif.clk);
  vif.valid<=1'b0;
  phase.drop_objection(this);
endtask
`endif

my_if.sv

`ifndef MY_IF__SV
`define MY_IF__SV

interface my_if(input clk ,input rst_n);
  logic [7:0]data;
  logic valid;
endinterface
`endif

top_tb.sv

`include "uvm_macros.svh"

import uvm_pkg::*;
`include "my_if.sv"
`include "my_driver.sv"
`include "dut.sv"
module top_tb;

reg clk;
reg rst_n;
reg[7:0]rxd;
reg rx_dv;
wire [7:0]txd;
wire tx_en;

my_if input_if(clk, rst_n);
my_if output_if(clk, rst_n);
dut my_dut(
      .clk(clk),
      .rst_n(rst_n),
      .rxd(input_if.data),
      .rx_dv(input_if.valid),
      .txd(output_if.data),
      .tx_en(output_if.valid)
    );
initial begin
  clk=0;
  forever begin
    #100 clk=~clk;
  end
end

initial begin
  rst_n=1'b0;
  #1000;
  rst_n=1'b1;
end

initial begin
  run_test("my_driver");
end
initial begin
  uvm_config_db#(virtual my_if)::set(null,"uvm_test_top","vif",input_if);
end
endmodule

makefile

UVM_HOME	= ../../../../../uvm-1.1d #uvm-1.1d的位置，  ../为退到上一级文件夹


all: clean comp run

comp:
	$(VCS) +incdir+. \
		top_tb.sv


run:
	$(SIMV)
	$(CHECK)

TEST = /usr/bin/test
UVM_VERBOSITY=UVM_LOW
N_ERRS = 0
N_FATALS = 0
# -fsdb_old    -ntb_opts 
//VCS =	vcs -sverilog -ntb_opts -timescale=1ns/1ns
VCS =	vcs -sverilog -timescale=1ns/1ns \
	+acc +vpi \
	+define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR \
	+incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm.sv \
	$(UVM_HOME)/src/dpi/uvm_dpi.cc -CFLAGS -DVCS

SIMV = 	./simv +UVM_VERBOSITY=$(UVM_VERBOSITY) -l vcs.log

URG  = urg -format text -dir simv.vdb

CHECK = \
	@$(TEST) \( `grep -c 'UVM_ERROR :    $(N_ERRS)' vcs.log` -eq 1 \) -a \
		 \( `grep -c 'UVM_FATAL :    $(N_FATALS)' vcs.log` -eq 1 \)

clean:
	rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log 
	

在terminal中输入make all

结果为