我的第一个FPGA小程序---测占空比

module	capt(
				clk,
				rst_n,
				//disabled,
				
				catin,
				PonTemp,
				Poff_reg
				);

input	clk,rst_n,catin;
output	PonTemp,Poff_reg;

//reg[16:0] value;
//output [7:0] segdata;
//output [2:0] segcs;

//reg		[16:0]	PonTemp;//PoffTemp;//char:256 max,data temp
//reg		[15:0]	Pon,Poff;

//首先对脉冲输入进行同步处理
reg		syn1;
reg		syn2;
always @ (posedge clk)
begin
		syn1 <= catin;
		syn2 <= syn1;
end

wire	catin_pos;
//获得输入脉冲的上升沿
assign	catin_pos = syn1 & (~syn2);

//计算高低电平宽度
reg	[16:0]	Pon_reg,PonTemp,Poff_reg;
wire	reset = (~rst_n);
always @ (posedge reset or posedge clk)
begin
	if(reset)
		 begin
		    
			Pon_reg <= 16'd0;
			Poff_reg <= 16'd0;
			
			//Pon <= 16'd0;
			//Poff <= 16'd0;
		 end
	else if(catin_pos)
		 begin
			//Pon <= Pon_reg;
			//Poff <= Poff_reg;
			if(Pon_reg !== 16'b0)
			    PonTemp <= (((Pon_reg)*1000)/(Pon_reg+Poff_reg))+1;
			Pon_reg <= 16'd0;
			Poff_reg <= 16'd0;
		 end
	else if(syn1)
		 begin
		  Pon_reg <= Pon_reg + 1'b1;
		  //fre_reg = Pon_reg + Poff_reg;
		 end
	else
		 begin
		  Poff_reg <= Poff_reg + 1'b1;
		  //fre_reg = Pon_reg + Poff_reg;
		 end
end
 

endmodule				



module SEG7(
				 clk_50M,
				 rst_n,
				
				 singal_in,
				 //tenvalue,
				 segdata,
				 segcs
			  );

input clk_50M,rst_n,singal_in;
//wire[16:0] tenvalue;

output [7:0] segdata;
output [2:0] segcs;

reg[24:0] count1ms,clk_100k;
reg[31:0] count;
reg clk1ms;
wire[16:0] tenvalue;
reg[2:0] number;
reg[2:0] segcs;
reg[7:0] segdata;
wire rst_n;
wire Pon_reg,Poff_reg;


/*
 *获取1MS的信号
 */
always@(posedge clk_50M)
  begin 
    if(count1ms>25'd1000_0)//1ms的时间
      begin
	      clk1ms<=~clk1ms;
	      count1ms<=0;
      end
    else
      count1ms<=count1ms+1;
  end		
		

always@(posedge clk1ms)
	 begin
		 if(count < 4'd5)
			 count <= count+1'b1;
		 else
			 begin
				count <= 0;
				clk_100k <= ~clk_100k;
			 end
	 end
				
		
		
		
/***********2进制转十进制函数*************/
function[7:0] tendata;//返回一个4位的数字
input[7:0]   datain;
begin
 case(datain)
		    4'b00000000: tendata=4'd0;//0
		    4'b00000001: tendata=4'd1;//1
		 	4'bd00000010: tendata=4'd2;//2
		    4'b00000011: tendata=4'd3;//3
		    4'b00000100: tendata=4'd4;//4
		    4'b00000101: tendata=4'd5;//5
		    4'b00000110: tendata=4'd6;//6
		    4'bd00000111: tendata=4'd7;//7
		    4'b00001000: tendata=4'd8;//8
		    4'b00001001: tendata=4'd9;//9
		    4'b00001010: tendata=4'd10;//
		    4'b00001011: tendata=4'd11;//
		    4'b00001100: tendata=4'd12;
		    4'b00001101: tendata=4'd13;
		    4'b00001110: tendata=4'd14;
		    4'b00001111: tendata=4'd15;
		    default:tendata=4'bzzzz_zzzz;
 endcase
end
endfunction


/*********十进制转LED段选函数*********/
function[7:0] leddata;//返回一个8位的数字
input[3:0]    datain;
	 begin
		  case(datain)
		    4'd0: leddata=8'b11000000;//0
		    4'd1: leddata=8'b11111001;//1
		 	4'd2: leddata=8'b10100100;//2
		    4'd3: leddata=8'b10110000;//3
		    4'd4: leddata=8'b10011001;//4
		    4'd5: leddata=8'b10010010;//5
		    4'd6: leddata=8'b10000010;//6
		    4'd7: leddata=8'b11111000;//7
		    4'd8: leddata=8'b10000000;//8
		    4'd9: leddata=8'b10010000;//9
		    4'd10: leddata=8'b10111111;//-
		    4'd11: leddata=8'b01111111;//.
		    default:leddata=8'bzzzz_zzzz;
		   endcase
	 end
endfunction


/********扫描函数*************/
always@(posedge clk_100k)
 begin
    if(number==5) 
    	number<=0;
    else 
    begin 
	    number<=number+1;
	    
	    case(number) 
	     4'd0:
	        begin
		        segdata<=leddata((tenvalue/10)%10);//个位
		        segcs<=3'b011;
	        end
	     4'd1:
	        begin
		        segdata<=leddata((tenvalue/100)%10);//十位
		        segcs<=3'b010;
	        end
	     4'd2:
	        begin
		        segdata<=leddata((tenvalue/1000)%10); //百位
		        segcs<=3'b001;
	        end
	     4'd3:
	        begin
		        segdata<=leddata(tenvalue/10000);//千位
		        segcs<=3'b000;
	        end
	     4'd4:
	        begin
		        segdata<=leddata(4'd11);//.
		        segcs<=3'b101;
	        end
		 endcase
	 end
end    

capt mycapt(
		.clk(clk_50M),
		.rst_n(rst_n),
		//disabled,
		
		
		.catin(singal_in),
		.PonTemp(tenvalue)
		//.Poff_reg(Poff_reg)
);

endmodule 		

        学了几天的FPGA，终于要入门了，不过语法还不过关，这个verilog程序测占空比，在至芯ZX-2上测试成功，还有很多bug,先记录一下我此时菜的FPGA手法，哈哈哈哈！