数码管显示电路的Verilog HDL实现

想用FPGA控制4位8段数码管分别显示数字1、2、3、4。假设位选信号为低有效，当位选有效时，段选为0对应的二极管段被点亮。程序如下：

module LED_Display(clk,seg,dp,an);

       input clk;        //输入时钟

       output[6:0] seg;      //7个公共段选信号，从低到高对应七段数码管的ABCDEFG

       output dp;       //小数点段选信号DP

       output[3:0] an;              //4位数码管的位选信号

 

       reg[15:0] count_for_clk=0;   //分频计数器

       reg[3:0] an_reg=0;

       reg[6:0] seg_reg=0;

 

       assign seg=seg_reg;       //7个段选赋值

       assign dp=1;          //小数点段选赋值

       assign an=an_reg;          //4个位选赋值

      

       parameter              //七段数码管显示数字0-9的段选值

              zero=7’b100_0000;

              one=7’b100_0000;

              two=7’b100_0000;

              three=7’b100_0000;

              four=7’b100_0000;

              five=7’b100_0000;

              six=7’b100_0000;

              seven=7’b100_0000;

              eight=7’b100_0000;

              nine=7’b100_0000;

 

       //分频计数器

       always@(posedge clk) begin

              count_for_clk<=count_for_clk+1;

       end

 

       //段选寄存器赋值，4位数码管分时复用

       always@(posedge clk) begin

              case(count_for_clk[15:14])

                     0:    seg_reg<=one;              //数码管1段选

                     1:    seg_reg<=two;       //数码管2段选

                     2:    seg_reg<=three;     //数码管3段选

                     3:    seg_reg<=four;      //数码管4段选

              endcase

       end

 

       //位选寄存器赋值，每次只能选通一位数码管

       always@(posedge clk) begin

              case(count_for_clk[15:14])

                     0:    an_reg<=4’b0111; //选通数码管1

                     1:    an_reg<=4’b1011;        //选通数码管2

                     2:    an_reg<=4’b1101;        //选通数码管3

                     3:    an_reg<=4’b1110; //选通数码管4

              endcase

       end