4位全加器结构化描述

//一位半加器的描述
module halfadder(input A,B,
                 output S,C
                 );
xor(S,A,B);
and(C,A,B);
endmodule

//一位全加器的描述
module fulladder(input A,B,Ci,
                 output Sum,Co
                 );
wire S1,D1,D2;
halfadder HA1(.B(B),.A(A),.S(S1),.C(D1));
halfadder HA2(.B(Ci),.A(S1),.S(Sum),.C(D2));
or g1(Co,D2,D1);
endmodule

//四位全加器的描述
module cy4(input[3:0] A,B,
           input C_1,
           output[3:0] S,
           output C3
           );
wire C0,C1,C2;
fulladder U0_FA(A[0],B[0],C_1,S[0],C0);
fulladder U1_FA(A[1],B[1],C0,S[1],C1);
fulladder U2_FA(A[2],B[2],C1,S[2],C2);
fulladder U3_FA(A[3],B[3],C2,S[3],C3);
endmodule

测试脚本代码：

`timescale 1 ns/ 1 ps
module cy4_vlg_tst();
reg [3:0] A;
reg [3:0] B;
reg C_1;                                              
wire C3;
wire [3:0]  S;

cy4 i1 (  
    .A(A),
    .B(B),
    .C3(C3),
    .C_1(C_1),
    .S(S)
);
initial                                                
begin                                                  
A = 4'b0000;
B = 4'b0001;
C_1 = 1'b1;
#5;
A = 4'b0010;
B = 4'b0010;
C_1 = 1'b1;
#5;
A = 4'b0011;
B = 4'b0011;
C_1 = 1'b1;
#5;
A = 4'b0100;
B = 4'b0100;
C_1 = 1'b1;
#5;
A = 4'b0101;
B = 4'b0101;
C_1 = 1'b1;
#5;
A = 4'b0110;
B = 4'b0110;
C_1 = 1'b1;
#5;
A = 4'b0111;
B = 4'b0111;
C_1 = 1'b1;
#5;
A = 4'b1000;
B = 4'b1000;
C_1 = 1'b1;
#5;
A = 4'b1001;
B = 4'b1001;
C_1 = 1'b1;
#5;
A = 4'b1010;
B = 4'b1010;
C_1 = 1'b1;
#5;
A = 4'b1011;
B = 4'b1011;
C_1 = 1'b1;
#5;
A = 4'b1100;
B = 4'b1100;
C_1 = 1'b1;
#5;
A = 4'b1101;
B = 4'b1101;
C_1 = 1'b1;
#5;
$stop;                                           
$display("Running testbench");                       
end                                                                                                     
endmodule