spartan6—clocking wizard_时钟输出接普通I/O口遇到的问题及解决方案
设计任务：调用spartan6—clocking wizard的IP核，完成时钟从100M到10M的转换
开发环境：
XP系统下
编译环境：ISE12.2/SP3，ISE(XST)综合工具通过综合
仿真环境：ISE12.2/SP3，自带的仿真工具仿真
顶层代码如下：
module clocking_top(clk,rst,clk_out,locked);
input clk,rst;
output clk_out,locked;
myclocking duwwe//这里命名不能为数字
(// Clock in ports
.CLK_IN1 (clk), // IN
// Clock out ports
.CLK_OUT1 (clk_out), // OUT
// Status and control signals
.RESET (rst), // IN
.LOCKED (locked)); // OUT
endmodule
激励文本如下：
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
#100；//这里rst拉低的时间注意，必须大于时钟的三个周期，否则locked 输出会是高阻态
rst = 0；
end
always #5 clk=~clk;
仿真结果：
综合通过，但有一个小的警告，可以忽略不会有什么影响。
引脚分布如下图：
（其中的clk1既是clk_out的输出引脚）
接下来进行了执行的时候出错了
map的时候生成下面的错误。
WARNING:Place:1205 - This design contains a global buffer instance,
< PIN: dsp_clkin.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
WARNING:Place:1205 - This design contains a global buffer instance,
< PIN: dsp_aeclkin.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance,
the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance,
the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
经过一番研究后明白是什么原因了，原来出错的关键是因为时钟输出直接接在I/O上。按照其中的说法：实例化一个ODDR2，这个小元件的详细介绍在xilinx参考文档ug381中有详细介绍。
这个贴出ODDR2模块的关键信息，如下两图说是：
实例化的代码是这样的：
ODDR2 #(
// The following parameters specify the behavior
// of the component.
.DDR_ALIGNMENT("NONE"), // Sets output alignment
// to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q
// output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
// set/reset
)
ODDR2_inst (
.Q(oddr2_xxxmhz), // 1-bit DDR output data
.C0(clkout1), // 1-bit clock input
.C1(~clkout1), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
信号oddr2_xxxmhz就是那个可以输出到普通IO的信号了。
参考上述代码修改后的顶层代码如下：
module clocking_top(clk,rst,clk_out,locked);
input clk,rst;
output clk_out,locked;
wire clk1;
myclocking duwwe//这里命名不能为数字
(// Clock in ports
.CLK_IN1 (clk), // IN
// Clock out ports
.CLK_OUT1 (clk1), // OUT
// Status and control signals
.RESET (rst), // IN
.LOCKED (locked)); // OUT
ODDR2 #(
// The following parameters specify the behavior
// of the component.
.DDR_ALIGNMENT("NONE"), // Sets output alignment
// to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q
// output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
// set/reset
)
ODDR2_inst (
.Q(clk_out), // 1-bit DDR output data
.C0(clk1), // 1-bit clock input
.C1(~clk1), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule
这样Implement就可以成功通过了！