vivado学习实验5笔记
1、实验内容：Xilinx Design Constraints设计约束
You will start the project with I/O Planning type, enter pin locations, and export it to the rtl. You will then create the timing constraints and perform the timing analysis创建一个I/O Planing类型的工程，输入相应管脚位置，然后将它输入rtl，再创建一个时序约束，并进行时序分析
2、设计描述：The design consists of a uart receiver receiving the input typed on a keyboard and displaying the binary equivalent of the typed character on the 8 LEDs. When a push button is pressed, the lower and upper nibbles are swapped. 串口接收器，用来接收来自键盘的数据，并以二进制形式在8个LED灯上显示出来，当一个按键按下来时，高位和低位互换
3设计流程：
第一步：创建一个I/O Planning 工程（以前建的是RTL工程）
创建好后的界面：device 和package pins
第二步：Assign Various Pins and Add Source Files分配不同的引脚并添加source files
2.1Assign input pins clk_pin, btn_pin, rxd_pin, and rst_pin to Y9, T18, Y10,
and P16 locations using the Device view and packagepins. 通过device和package pins 来手动分配输入引脚
2.2Assign output pins led_pins[7] to led_pins[0] to U14, U19, W22, V22, U21,
U22, T21, and T22 locations creating them as a vector and assigning them
using Tcl command set_propoerty. They all will be LVCMOS33. 创建一个向量led_pins,并用Tcl command设置属性，用来分配输出引脚，如：
set_property PACKAGE_PIN T22 [get_ports led_pins[0]]
set_property PACKAGE_PIN T21 [get_ports led_pins[1]]
set_property PACKAGE_PIN U22 [get_ports led_pins[2]]
set_property PACKAGE_PIN U21 [get_ports led_pins[3]]
set_property PACKAGE_PIN V22 [get_ports led_pins[4]]
set_property PACKAGE_PIN W22 [get_ports led_pins[5]]
set_property PACKAGE_PIN U19 [get_ports led_pins[6]]
set_property PACKAGE_PIN U14 [get_ports led_pins[7]]
Select File > Save Constraints：保存constraints
migrate to RTL:(则进入rtl，uart_led.v保存进source file)
2.3Add the provided source files (from c:\xup\fpga_flow\sources\lab5) to the
project. Copy the uart_led.txt (located in the
c:\xup\fpga_flow\sources\lab5) content into the top-level source file.添加一些源文件
第三步：Synthesize and Enter Timing Constraints 合成设计并添加时序约束
Synthesize后——Select Synthesis > Synthesized Design > Edit Timing Constraints in the Flow Navigator pane在synthesize下面编辑时序约束
设计clock约束clk_pin
设计input约束Assign Input Setup Delay of 0 ns to the btn_pin, rxd_pin, and rst_pin input with respect to the clk_pin port设置输入setup delay为0 ns
Assign -0.5 ns as the minimum hold time on the btn_pin, rxd_pin, and rst_pin input with respect to the clk_pin port设置最低保持时间-0.5 ns
Assign 0 ns as the output delay on the led_pins (all eight) output with respect to the clk_pin port设置输出led_pins延迟为0 ns
Generate an estimated Timing Report showing both the setup and hold paths in the design产生一个估计的时间约束报告显示了setup and hold paths（其中report timing summary中，分为三个组合group：setup、hold、pulse width——The Design Timing Summaryreport provides a brief worst Setup and Hold slack information）（修改连线中的错误）
第三步：Implement and Analyze Timing Summary实现设计和分析时序
Implement the design实现设计
Generate a timing summary report产生时序报告
第四步：Generate the Bitstream and Verify the Functionality产生.bit流并确认功能
（正在购买PmodUSBUart module。。。）