《Low power design essential》读后笔记(二)

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chapter 2

1. sub-100 nm

• leakage behavior of the transistor

• variability

• innovative devices

summarized as follow:
a linear dependence exists between voltage and current; threshold is a function of channel length and operational voltages.

2. $I_D-V_{DS}$

velocity-saturation effect

decrease in output resistance of the device in saturation
Reason:

• channel-length modulation
• drain-induced barrier lowering(DIBL) which is also related to a reduction of the threshold voltage
• SCBE(Substrate Current Body Effect)

Model:

• $$I_{Dsat}={\upsilon }_{Sat}W{C}_{ox}\frac{(V_{GS}-V_{TH}{)}^2}{(V_{GS}-V_{TH})+E_{C}L}$$ $E_C$ the critical electrical field

• the unified model
  $$\{\begin{array}{l}{I}_D=0for{V}_{GT}\le 0\\ I_D=k^{’}\frac{W}{L}(V_{GT}{V}_{min}-\frac{V_{min}^2}{2})(1+\lambda V_{DS})for{V}_{GT}\ge 0where{V}_{min}=min(V_{GT},V_{DS},V_{Dsat})\\ V_{GT}=V_{GS}-V_{TH}\\ V_{TH}=V_{TH0}+\gamma (\sqrt{|-2{\varphi }_F+V_{SB}|}-\sqrt{|-2{\varphi }_F|})\end{array}$$

  $V_{Dsat}$ is a fixed voltage

• alpha model
  $$I_{DS}=\frac{W}{2L}\mu C_{ox}(V_{GS}-V_{TH}{)}^{\alpha }$$

3. Threshold

use the extrapolation technique

not a constant $V_{SB}$ can be used to control $V_{TH}$

• The foremost is the body-bias or back-bias effect $\gamma$

• channel length (short channel) shorter channel, smaller threshold

  solutions: “halo implants” increases the threshold

• DIBL: drain voltage influences the threshold
  $$V_{TH}=V_{TH0}-{\lambda }_d{V}_{DS}$$

4. sub-threshold drain-source effects

below 180 nm level

Reason:

• an exponential function of $V_{GS}$ which is also influenced by ${\gamma }_d$ and ${\lambda }_d$
• “Gate-induced drain leakage(GIDL)” when $V_G$ is negative
  larger in NMOS than PMOS
  minor effect compare with DIBL

5. gate leakage

below 100 nm level

normally, the gate oxide(SiO2) thickness is scaled as well. cause a reduction in the gate resistance of the transistor

Reason:

• Fowler-Nordheim(FN) tunneling

• direct-oxide tunneling dominant

  exponentially with respect to both of these parameters

solutions:

• stop or slow down the scaling of oxide thickness

example:

keep the current the same while increase the thickness of the gate

$$k^{’}=\mu C_g=\mu ϵ/t_g$$

high-$k$ gate replace SiO2 with high-$k$ material

“equivalent oxide thickness” (EOT) = $T_g\times ({ϵ}_{ox}/{ϵ}_g)$

6. temperature influence

temperature rises, mobility reduces, $V_{TH}$ reduces.

$I_{on}$ decreases, $I_{off}$ increases

7. variability

worst-case corners(FF, SS, FS, SF) cause flunctations

low-power design: lower $V_{DD}/V_{TH}$, smaller SNR worse variability

Reason:

• physical

• manufacturing dominant

• environmental solution: package

• operational

8. innovations:

• strained silicon increase the mobility in CMOS SiGe PMOS effects better than NMOS

  $V_{TH}$ increases at the same time , $I_{on}$ increase, $I_{off}$ decrease

• Silicon-on-insulator (SOI) have thin silicon layer

  • junction capacitances are reduced power saving

  • higher sub-threshold slope factor reduce leakage

  • sensitivity to soft errors

  example: PD-SOI(partially-depleted) FD-SOI(fully-depleted)

• FD-SOI with a buried gate control threshold

• FinFET improve the effective channel length of the device SOI substrate

  example: Double-gated(DG) MOSFET Back-gated(BG) MOSFET

• CNT(carbon-nanotube)

• I-MOS

• MEMS